Senior FPGA Timing Engineer – STA & Closure Lead

Altera Corporation; San Jose, Northern (CA, KY); Hybrid; USD 119,000 - 172,000; Full time

Job summary

Altera Corporation in San Jose, California, is seeking a Timing Engineer to lead timing activities across a subsystem, partnering with Design, Architecture and Physical Design to achieve timing convergence from implementation to sign-off.

The role requires strong STA, timing constraints, and advanced sign-off methods, with experience on modern process nodes; you will drive timing budgets, clock planning, and ECOs, and collaborate with RTL, PD and full-chip teams.

Qualifications

• 5+ years of ASIC/FPGA timing analysis and sign-off.
• Experience with timing constraints and STA methodologies.

Responsibilities

• Drive timing closure at block level and sub-system level.
• Develop methodology through flow/scripting for easier interface timing closure.
• Define and manage I/O timing budgets across hierarchical designs.
• Apply advanced sign-off methodologies including POCV/POPV effects.
• Provide timing feedback with root-cause analysis and ECO guidance.
• Coordinate large-scale multi-corner/multi-mode STA runs with automation.
• Generate and validate timing ECOs with PD/RTL teams.
• Plan clock trees and clock architecture for easier timing closure.

Skills

Static timing analysis

Synthesis/Place-and-Route

Scripting (Python/Tcl/Perl)

Cross-functional collaboration

Problem solving

Education

Bachelor's degree in Electrical/Computer Engineering

Tools

Cadence Tempus

Synopsys PrimeTime

Job description

Altera Corporation in San Jose, California, is seeking a Timing Engineer to lead timing activities across a subsystem, partnering with Design, Architecture and Physical Design to achieve timing convergence from implementation to sign-off.

The role requires strong STA, timing constraints, and advanced sign-off methods, with experience on modern process nodes; you will drive timing budgets, clock planning, and ECOs, and collaborate with RTL, PD and full-chip teams.