Senior SoC Timing Signoff Engineer

Aleron; San Diego (CA); On-site; USD 120,000 - 160,000; Full time

Benefits offered by this job

Supportive team-driven culture

Career growth opportunities

People-first environment

Job summary

Aleron in San Diego, CA, is seeking a Senior SoC STA Engineer to lead chip-level timing sign-off for next-generation SoC designs. This senior technical role focuses on static timing analysis and timing closure while collaborating with multiple teams to ensure timing integrity.

The ideal candidate will possess at least 6 years of hands-on experience, expertise in STA tools like Cadence Tempus, and a strong educational background in electrical engineering. Join a team that values innovation and professional growth!

Qualifications

• Minimum 6 years of experience in chip-level STA ownership.
• Deep expertise in full timing sign-off across multiple tape-outs.
• Proven experience with SDC constraints for large SoCs.

Responsibilities

• Own end-to-end chip-level static timing analysis and sign-off.
• Develop and maintain sign-off-quality SDC constraints.
• Drive timing closure through critical path analysis.

Skills

Chip-level STA ownership

Static timing analysis (STA)

Advanced timing concepts

Python scripting

Tcl scripting

Education

Bachelor’s degree in Electrical Engineering or related discipline

Master’s degree (preferred)

Tools

Cadence Tempus

Job description

Aleron in San Diego, CA, is seeking a Senior SoC STA Engineer to lead chip-level timing sign-off for next-generation SoC designs. This senior technical role focuses on static timing analysis and timing closure while collaborating with multiple teams to ensure timing integrity.

The ideal candidate will possess at least 6 years of hands-on experience, expertise in STA tools like Cadence Tempus, and a strong educational background in electrical engineering. Join a team that values innovation and professional growth!