Senior STA & Constraints Engineer – Timing Closure for SoC

AMD; Santa Clara (CA); On-site; USD 120,000 - 190,000; Full time

Job summary

AMD is seeking a STA/Constraints Engineer in Santa Clara, CA to own end‑to‑end timing constraints and closure for SOCs and sub‑systems. You will work with Fellows, Principal Engineers and architects, guiding RTL designers and PD teams across cross‑functional global groups.

The role requires expertise in STA, timing signoff, and PD tooling (SNPS PT/GCA, ICC2/FC), Verilog RTL, and scripting. You’ll contribute to robust clock design, SDC development, and power-aware implementations.

Qualifications

• Experience in STA, constraints, timing signoff and physical design.
• Proficient with PD tools such as SNPS PT/GCA and ICC2/FC.
• Strong Verilog RTL design experience.
• Scripting skills in Python/TCL/Perl.
• Excellent communication and cross‑functional collaboration skills.

Responsibilities

• Own end‑to‑end delivery of designs from timing constraints and timing signoff.
• Collaborate with SOC Architecture team for clocks and timing targets.
• Set up clocks and constraints in SDC and ensure correct implementation.
• Understand timing margins and work with timing teams for current and future projects.
• Define design requirements, milestones, and deliver FCT closure.
• Coordinate with CAD/EDA vendors to strengthen timing closure processes.
• Ensure CDC/LINT, timing closure, and low‑power implementation quality.
• Work on SDC development and Clock Domain Crossing strategies.

Skills

STA experience

Timing signoff

Physical design

PD tools (SNPS PT/GCA)

Verilog RTL

Scripting (Python/TCL)

DFT timing concepts

Clock domain crossing

Education

Bachelor/Master in Microelectronics

Tools

SNPS PT/GCA

ICC2/FC

Job description

AMD is seeking a STA/Constraints Engineer in Santa Clara, CA to own end‑to‑end timing constraints and closure for SOCs and sub‑systems. You will work with Fellows, Principal Engineers and architects, guiding RTL designers and PD teams across cross‑functional global groups.

The role requires expertise in STA, timing signoff, and PD tooling (SNPS PT/GCA, ICC2/FC), Verilog RTL, and scripting. You’ll contribute to robust clock design, SDC development, and power-aware implementations.