Senior FPGA Timing Engineer - Convergence Lead

Altera; San Jose (CA); On-site; USD 119,000 - 172,000; Full time

Job summary

Altera is seeking a Timing Engineer to join our Physical Design organization in San Jose, CA. You will lead timing activities for a subsystem, partnering with Design, Architecture, and Physical Design teams to achieve timing convergence from implementation through final sign-off.

The ideal candidate brings strong static timing analysis expertise, timing constraints experience, and a track record in advanced process technologies.

Qualifications

• Bachelor's degree in Electrical Engineering or related field.
• 5+ years in ASIC/FPGA timing analysis and sign-off.
• Experience with STA, timing constraints, and full-chip timing closure.
• Experience with synthesis, place-and-route, and parasitic extraction.
• Experience with 5nm or below nodes including OCV/POCV/POCV analysis.
• 5+ years of MCMM timing analysis experience.
• Proficient with Cadence Tempus and Synopsys PrimeTime.
• Experience scripting with Tcl/Python/Perl.

Responsibilities

• Drive timing closure at block and sub-system levels.
• Develop methodology through flow and scripting for easier interface timing closure.
• Define and manage I/O timing budgets across hierarchical designs.
• Apply advanced sign-off methodologies at lower nodes (POCV/OCV/PVT).
• Provide timing feedback with root-cause analysis and ECO guidance.
• Manage large-scale multi-corner/multi-mode STA runs with automation.
• Generate and validate timing ECOs with RTL and physical design teams.
• Global clock planning to simplify interface timing closure.
• Collaborate with design, implementation, and full-chip teams for sign-off.

Skills

Static Timing Analysis

Timing closure

Scripting (Tcl)

Scripting (Python)

Scripting (Perl)

Cadence Tempus

Synopsys PrimeTime

MCMM timing analysis

ASIC/FPGA timing

Root Cause Analysis

RTL collaboration

Education

Bachelor's degree in Electrical Engineering or related

Tools

Cadence Tempus

Synopsys PrimeTime

Tcl scripting

Python scripting

Perl scripting

Job description

Altera is seeking a Timing Engineer to join our Physical Design organization in San Jose, CA. You will lead timing activities for a subsystem, partnering with Design, Architecture, and Physical Design teams to achieve timing convergence from implementation through final sign-off.

The ideal candidate brings strong static timing analysis expertise, timing constraints experience, and a track record in advanced process technologies.