Physical Design Implementation and STA Lead

Altera; San Jose (CA); On-site; USD 149,100 - 215,000; Full time

Job summary

Altera is seeking an experienced Physical Design Implementation & STA Lead to drive floorplanning, synthesis, CTS, and ECO closure for next‑generation FPGA SoCs. You will lead physical design implementation and static timing analysis activities for complex blocks and SoC subsystems, coordinating with RTL, DFT, CAD, packaging, and library teams.

This highly technical individual contributor role includes mentoring engineers, developing Tcl and Python automation, and advancing reusable

Qualifications

• 7+ years in physical design, physical implementation, or SoC backend development.
• 5+ years in block‑level physical implementation including synthesis, floorplanning, place‑and‑route, clock tree synthesis.

Responsibilities

• Lead block-level physical implementation including synthesis, floorplanning, place‑and‑route, CTS, optimization, and ECO closure.
• Support SoC-level physical implementation and collaborate on floorplanning, partitioning, and integration strategies.
• Develop and maintain implementation constraints including SDC and UPF to achieve timing, power, and area goals.
• Partner with RTL, DFT, CAD, packaging, and library teams to resolve implementation issues throughout the design cycle.
• Drive implementation convergence across timing, power, congestion, and routability objectives.
• Lead STA and timing closure across multiple process, voltage, and temperature corners (MMMC).
• Perform timing analysis using PrimeTime or equivalent STA tools.
• Develop timing constraints and validate timing exceptions to ensure robust signoff quality.

Skills

Physical design

STA

Floorplanning

Place-and-route

Synthesis

CTS

Timing closure

ECO closure

Python automation

Tcl scripting

Education

Bachelor's degree in Electrical Engineering or Computer Engineering

Tools

PrimeTime

CAD tools

Python/Tcl scripting

Job description

Job Details

Job Description: About Altera – At Altera, our independence as the world's largest pure‑play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry‑leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely—empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.

About the Role

We are seeking an experienced Physical Design Implementation & Static Timing Analysis (STA) Lead to play a key technical role in delivering high‑quality physical implementation and timing closure for next‑generation FPGA SoCs. In this role, you will lead physical design implementation and static timing analysis activities for complex blocks and SoC subsystems, driving implementation from floorplanning through final timing closure while partnering closely with RTL, architecture, DFT, CAD, and signoff teams. This is a highly technical individual contributor role with project leadership responsibilities. You will provide technical guidance to engineers across implementation and timing closure activities while helping improve methodologies and evaluating emerging ML/AI‑assisted physical design technologies.

Key Responsibilities

• Lead block‑level physical implementation including synthesis, floorplanning, place‑and‑route, clock tree synthesis (CTS), optimization, and ECO closure.
• Support SoC‑level physical implementation and collaborate on floorplanning, partitioning, and integration strategies.
• Develop and maintain implementation constraints including SDC and UPF to achieve timing, power, and area (PPA) goals.
• Partner with RTL, DFT, CAD, packaging, and library teams to resolve implementation issues throughout the design cycle.
• Drive implementation convergence across timing, power, congestion, and routability objectives.
• Contribute to methodology improvements and implementation best practices.
• Lead static timing analysis (STA) and timing closure across multiple process, voltage, and temperature corners (MMMC).
• Perform timing analysis using Synopsys PrimeTime or equivalent STA tools.
• Identify and resolve setup, hold, recovery, removal, SI/crosstalk, and clock‑related timing violations.
• Drive timing‑driven ECO implementation in collaboration with RTL and physical design teams.
• Develop timing constraints and validate timing exceptions to ensure robust signoff quality.
• Partner with library, CAD, and methodology teams to improve timing closure efficiency.
• Execute signoff activities including IR drop, electromigration (EM), DRC, LVS, antenna, and physical verification.
• Analyze congestion, routing quality, clock quality, and PPA tradeoffs.
• Support implementation planning to achieve project schedules and tapeout milestones.
• Utilize ML/AI‑assisted implementation technologies to improve timing closure and physical design productivity.
• Develop Tcl and Python automation to streamline implementation and timing analysis workflows.
• Collaborate with CAD teams to evaluate AI‑assisted optimization methodologies and next‑generation implementation flows.
• Analyze implementation metrics and timing data to identify optimization opportunities.
• Provide technical leadership for physical implementation and STA activities across one or more projects.
• Mentor junior and mid‑level physical design engineers on implementation and timing closure methodologies.
• Participate in design reviews, timing reviews, and signoff readiness meetings.
• Contribute to reusable methodologies, automation, and engineering best practices.

Qualifications

Minimum Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical discipline with 7+ years of industry experience in physical design, physical implementation, or static timing analysis, including the following:

• 7+ years of experience in physical design, physical implementation, or SoC backend development for advanced semiconductor products.
• 5+ years of experience performing block‑level physical implementation including synthesis, floorplanning, place‑and‑route, clock tree synth

Salary Range

$149,100 – $215,000 USD (Bay Area, California only; actual salary may vary based on location, experience, and other factors).