Senior FPGA Timing Engineer — STA & Automation

191 Altera Corporation; San Jose (CA); On-site; USD 119,000 - 172,000; Full time

Job summary

Altera is seeking a Timing Engineer to join its Physical Design team in San Jose, CA. You will lead timing activities and drive convergence from implementation through sign-off for FPGA subsystems.

The ideal candidate brings 5+ years of ASIC/FPGA timing analysis, strong STA knowledge, and scripting skills (Tcl/Python/Perl). Collaboration with RTL, Architecture, and PD teams is essential.

Qualifications

• Bachelor's degree in Electrical/Computer Engineering, CS or related field.
• 5+ years ASIC/FPGA timing analysis and sign-off experience.
• Experience with timing constraints, STA methodologies, and full-chip timing.
• Experience with synthesis, place-and-route, parasitic extraction flows.
• Experience with advanced semiconductor technologies (5nm or below).
• Experience MCMM timing analysis and using PrimeTime/Tempus.
• Experience developing automation and scripting (Tcl/Python/Perl).
• Collaborative work with RTL, Architecture, Physical Design, and Full Chip teams.

Responsibilities

• Drive timing closure at block and subsystem levels.
• Develop flow and scripting to ease interface timing closure.
• Define and manage I/O timing budgets across designs.
• Apply sign-off methodologies (POCV/POCV) at lower nodes.
• Provide timing feedback with root-cause analysis and ECO guidance.
• Run large MCMM STA tasks with automation and efficient resources.
• Generate and validate timing ECOs with PD and RTL teams.
• Plan clocks globally for easier interface timing closure.
• Collaborate across design, implementation, and full-chip teams.

Skills

Timing analysis

STA know-how

Problem solving

Independent work

Cross-functional collaboration

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Tools

Cadence Tempus

Synopsys PrimeTime

Tcl/Python/Perl scripting

Job description

Altera is seeking a Timing Engineer to join its Physical Design team in San Jose, CA. You will lead timing activities and drive convergence from implementation through sign-off for FPGA subsystems.

The ideal candidate brings 5+ years of ASIC/FPGA timing analysis, strong STA knowledge, and scripting skills (Tcl/Python/Perl). Collaboration with RTL, Architecture, and PD teams is essential.