Timing Engineer

191 Altera Corporation; San Jose (CA); On-site; USD 119,000 - 172,000; Full time

Job summary

Altera is seeking a Timing Engineer to join its Physical Design team in San Jose, CA. You will lead timing activities and drive convergence from implementation through sign-off for FPGA subsystems.

The ideal candidate brings 5+ years of ASIC/FPGA timing analysis, strong STA knowledge, and scripting skills (Tcl/Python/Perl). Collaboration with RTL, Architecture, and PD teams is essential.

Qualifications

• Bachelor's degree in Electrical/Computer Engineering, CS or related field.
• 5+ years ASIC/FPGA timing analysis and sign-off experience.
• Experience with timing constraints, STA methodologies, and full-chip timing.
• Experience with synthesis, place-and-route, parasitic extraction flows.
• Experience with advanced semiconductor technologies (5nm or below).
• Experience MCMM timing analysis and using PrimeTime/Tempus.
• Experience developing automation and scripting (Tcl/Python/Perl).
• Collaborative work with RTL, Architecture, Physical Design, and Full Chip teams.

Responsibilities

• Drive timing closure at block and subsystem levels.
• Develop flow and scripting to ease interface timing closure.
• Define and manage I/O timing budgets across designs.
• Apply sign-off methodologies (POCV/POCV) at lower nodes.
• Provide timing feedback with root-cause analysis and ECO guidance.
• Run large MCMM STA tasks with automation and efficient resources.
• Generate and validate timing ECOs with PD and RTL teams.
• Plan clocks globally for easier interface timing closure.
• Collaborate across design, implementation, and full-chip teams.

Skills

Timing analysis

STA know-how

Problem solving

Independent work

Cross-functional collaboration

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Tools

Cadence Tempus

Synopsys PrimeTime

Tcl/Python/Perl scripting

Job description

Job Details: Job Description: About Altera

At Altera™, our independence as the world’s largest pure‑play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry‑leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely—empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.

About the Role Altera is seeking a Timing Engineer to join our Physical Design organization. In this role, you will lead timing activities for a subsystem, partnering closely with the Design, Architecture, and Physical Design teams to achieve timing convergence from implementation through final sign-off. The ideal candidate brings strong expertise in static timing analysis (STA), timing constraints, and timing closure methodologies, with experience working on advanced process technologies. You will play a key role in driving subsystem timing closure, developing timing methodologies, and collaborating across engineering teams to deliver high-quality FPGA products.

Key Responsibilities

• Drive timing closure at block level and sub-system level.
• Developing methodology through flow/scripting which will result in easier interface timing closure at full chip.
• Define and manage I/O timing budgets across hierarchical designs.
• Apply advanced sign-off methodologies at lower nodes, including POCV and PVT effects.
• Provide actionable timing feedback at both block and sub-system levels, including root cause analysis and ECO guidance.
• Manage large-scale multi-corner/multi-mode STA runs with automation, partitioning, and efficient resource usage.
• Generate and validate timing ECOs, partnering with physical design and RTL teams for quick closure.
• Global clock planning for easier interface timing closure.
• Work closely with design, implementation, and full chip teams to drive timing convergence, providing sign-off level expertise and guidance.

Salary Range The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance. $118,900 - $172,000 USD

We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.

Minimum Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field and 5+ years of experience in ASIC or FPGA timing analysis and sign-off.
• 5+ years of experience in timing analysis, static timing analysis (STA), and timing sign-off.
• 5+ years of experience with timing constraints, STA methodologies, and timing closure at both the block and full-chip levels.
• 5+ years of experience with synthesis, place-and-route, and parasitic extraction flows.
• 5+ years of experience applying advanced timing concepts for leading-edge semiconductor technologies (5nm or below), including OCV, POCV, and PVT analysis.
• 5+ years of experience performing multi-corner, multi-mode (MCMM) timing analysis.
• 5+ years of experience using industry-standard timing analysis tools such as Cadence Tempus and Synopsys PrimeTime.
• 5+ years of experience developing automation and scripting solutions using Tcl, Python, and/or Perl.
• 5+ years of experience collaborating with RTL Design, Architecture, Physical Design, and Full Chip teams to drive timing closure.
• Demonstrated ability to work independently with strong prioritization, problem-solving, and solution-oriented decision-making skills.

Preferred Qualifications

• Experience with advanced FPGA or high-performance ASIC designs.
• Experience developing timing methodologies and automation for large-scale hierarchical designs.
• Experience defining hierarchical timing budgets and driving interface timing closure.
• Experience generating and validating timing ECOs during implementation and sign-off.
• Familiarity with clock tree synthesis (CTS), clock planning, and clock architecture optimization.
• Strong understanding of digital design fundamentals and physical implementation methodologies.
• Excellent analytical, debugging, and root cause analysis skills.
• Strong written and verbal communication skills with the ability to collaborate across multidisciplinary engineering teams.

Job Type: Regular Shift: Shift 1 (United States of America) Primary Location: San Jose, California, United States Additional Locations:

Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation or any other characteristic protected by local law, regulation or ordinance.

About Altera

Altera: Accelerating Innovators Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from cloud to edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation. Altera is helping to shape the future through pioneering innovation that unlocks extraordinary possibilities for everyone on the planet.