Principal Physical Design Engineer – Timing Convergence Lead

Asteralabs; San Jose (CA); On-site; USD 209,000 - 250,000; Full time

Job summary

Asteralabs in San Jose, California is seeking a Principal Physical Design Engineer to lead timing analysis and ensure robust timing convergence across complex ASIC designs used by top cloud service providers.

The ideal candidate should have a Bachelor's in Electrical Engineering or Computer Science, over 10 years of experience in SOC design and a strong command of STA methodologies. This is a fully on-site position and offers a competitive salary of USD 209,000 – USD 250,000 depending on experience.

Qualifications

• Over 10 years of experience in timing analysis and sign-off for complex SoCs in Server, Storage, or Networking applications.
• Expertise in timing constraints and timing closure, both at block and full-chip level.
• Familiarity with advanced nodes (7nm or below) is essential.

Responsibilities

• Drive timing closure from RTL through sign-off.
• Develop and validate SDC constraints for STA analysis.
• Manage I/O timing budgets across hierarchical designs.
• Generate and validate timing ECOs.

Skills

Timing analysis

STA methodology

Script writing (Tcl, Python, Perl)

Synthesis and place-and-route flows

Education

Bachelor’s in Electrical Engineering or Computer Science

Master’s degree (preferred)

Tools

Cadence

Synopsys

Job description

Asteralabs in San Jose, California is seeking a Principal Physical Design Engineer to lead timing analysis and ensure robust timing convergence across complex ASIC designs used by top cloud service providers.

The ideal candidate should have a Bachelor's in Electrical Engineering or Computer Science, over 10 years of experience in SOC design and a strong command of STA methodologies. This is a fully on-site position and offers a competitive salary of USD 209,000 – USD 250,000 depending on experience.