Senior FPGA/PCIe Solutions Architect

AMD; San Jose (CA); On-site; USD 140,000 - 210,000; Full time

Job summary

AMD is seeking a performant hardware/firmware engineer in San Jose to architect and implement cutting-edge ASIC/FPGA acceleration solutions. You will design high‑speed RTL, validate complex interfaces, and collaborate across global teams.

The role involves system-level integration, pre/post-silicon verification, and hands-on work with Vivado and UVM in a fast-paced environment. A strong background in digital design and compute acceleration is required.

Qualifications

• Experience in ASIC/FPGA design and verification.
• Strong knowledge of SystemVerilog/Verilog and timing closure.
• Familiarity with PCIe, CXL, DDR5/6 protocols.

Responsibilities

• Participate in all phases of product development from architecture to validation.
• Collaborate with hardware, firmware, and software teams to implement features.
• Develop high-performance hardware acceleration and embedded software controllers.

Skills

ASIC/FPGA design

SystemVerilog/Verilog

PCIe/CXL/DDR5/6

Python scripting

Documentation

Education

Bachelors or Masters in Computer Engineering or Electrical Engineering

Tools

Xilinx Vivado

UVM-based verification

Job description

AMD is seeking a performant hardware/firmware engineer in San Jose to architect and implement cutting-edge ASIC/FPGA acceleration solutions. You will design high‑speed RTL, validate complex interfaces, and collaborate across global teams.

The role involves system-level integration, pre/post-silicon verification, and hands-on work with Vivado and UVM in a fast-paced environment. A strong background in digital design and compute acceleration is required.