Senior FPGA/SoC Validation Engineer

AMD; San Jose (CA); On-site; USD 180,000 - 260,000; Full time

Benefits offered by this job

Benefits

Job summary

AMD is seeking an experienced FPGA/embedded systems engineer to design high-performance FPGA solutions and the accompanying software. The role spans exploration, architecture, RTL design, verification, and system bring-up across PCIe, memory interfaces, and video/AI workloads.

You will develop firmware for on-chip cores, build embedded Linux images with Yocto, and validate designs from pre-Si through board bring-up, collaborating with architects and hardware teams to deliver robust platforms.

Qualifications

• 8+ years in FPGA designs and related hardware/firmware work.

Responsibilities

• Take a technical role across every phase of the product cycle from exploration to bring-up and support.
• Collaborate with architects, hardware and firmware engineers to scope and implement features.
• RTL development in SystemVerilog/Verilog for high-performance IPs and interfaces like PCIe, LPDDR5/6, HDMI 2.1, USB3.1, UFS 4.0.
• Embed systems: write firmware and low-level software for ARM Cortex/RISC-V cores; build Yocto images and BSPs.
• System-level bring-up and validation using Vivado/Vitis ecosystems; pre-/post-Si verification and bench setup.

Skills

SystemVerilog

Verilog

VHDL

C/C++

Linux

Yocto

ARM/RISC-V

PCIe

Vivado/Vitis

NoC/SoC integration

Python/Tcl

Education

Bachelors or Masters in Computer/Electrical Engineering

Tools

Vivado

Vitis

EDAs / PCB design tools

Job description

AMD is seeking an experienced FPGA/embedded systems engineer to design high-performance FPGA solutions and the accompanying software. The role spans exploration, architecture, RTL design, verification, and system bring-up across PCIe, memory interfaces, and video/AI workloads.

You will develop firmware for on-chip cores, build embedded Linux images with Yocto, and validate designs from pre-Si through board bring-up, collaborating with architects and hardware teams to deliver robust platforms.