Senior FPGA SoC Solution Validation Engineer

Advanced Micro Devices; San Jose (CA); On-site; USD 120,000 - 180,000; Full time

Benefits offered by this job

AMD Benefits

Job summary

Advanced Micro Devices (AMD) in Santa Clara region offers a challenging role to design and validate FPGA-based systems. You will work on RTL for high-speed interfaces, embedded software, and system-level bring-up across multiple architectures including ARM and RISC-V cores.

You will collaborate across sites/time zones, perform pre-silicon verification, and drive board bring-up through validation and integration with Vivado/Vitis toolchains. Strong communication and mentoring skills are essential.

Qualifications

• 8+ years of hands-on FPGA designs.
• Strong SystemVerilog/Verilog and Vivado proficiency.
• Experience with high-speed interfaces and real-time systems.

Responsibilities

• Lead architecture, design, and validation of FPGA IPs across the product cycle.
• Collaborate with architects, hardware and firmware teams for feature scoping.
• RTL development in SystemVerilog/Verilog for PCIe, DDR5/6, USB, SerDes.
• Embed firmware and low-level system software for ARM/RISC-V cores.
• Perform pre/post-Si verification and board bring-up, validation.
• Develop System Level designs using Vivado/Vitis toolchains.

Skills

FPGA design

SystemVerilog

Verilog/VHDL

C/C++

Embedded Linux

Vivado

Board bring-up

Python/Tcl

Education

Bachelors or Masters in EE/Computer Engineering

Tools

Yocto

Git

Linux

HDL simulators

Job description

Advanced Micro Devices (AMD) in Santa Clara region offers a challenging role to design and validate FPGA-based systems. You will work on RTL for high-speed interfaces, embedded software, and system-level bring-up across multiple architectures including ARM and RISC-V cores.

You will collaborate across sites/time zones, perform pre-silicon verification, and drive board bring-up through validation and integration with Vivado/Vitis toolchains. Strong communication and mentoring skills are essential.