Senior FPGA Micro-Architect: Power, Performance, Innovation

Lattice Semiconductor Corp.; San Jose (CA); On-site; USD 225,000 - 275,000; Full time

Job summary

Lattice Semiconductor Corp. in San Jose, CA seeks a Principal FPGA Micro-Architect to define micro-architecture of fabric primitives and drive PPAU optimization across device families, targeting AI, robotics, data centers, and edge applications.

The ideal candidate has 15+ years of FPGA fabric experience, strong SystemVerilog/Verilog and SystemC/C++ modeling skills, and a proven track record from architecture through silicon validation.

Qualifications

• MS/PhD in Electrical or Computer Engineering with 15+ years of FPGA fabric micro-architecture experience.
• Proven track record delivering FPGA primitives from architecture through tape-out.
• Deep expertise in logic elements, DSP blocks, embedded memory, interconnect routing muxes, carry chains, and clocking structures.
• Proficiency in SystemVerilog/Verilog and SystemC/C++ architectural modeling for performance analysis and design trade-off evaluation.
• Extensive hands-on experience in silicon validation and post-silicon debug of FPGA fabric blocks, including bring-up and root-cause analysis.

Responsibilities

• Define micro-architecture of core fabric primitives: programmable logic elements, DSP blocks, embedded memory blocks, interconnect routing, configuration memory, carry chains, and clocking structures.
• Drive fabric PPAU optimization across device generations; evaluate implementation and routing feasibility and drive design trade-offs for modularity and scalability.
• Develop SystemC/C++ architectural models to drive performance analysis and evaluate fabric design trade-offs ahead of RTL/schematic availability.
• Lead advanced low-power fabric design including clock and power islands, power gating, dual-rail architectures, and dynamic power mode switching.
• Drive software primitive definition and implementation strategy, ensuring fabric elements are mapped to CAD tools and customer design flows for maximum usability.
• Partner with architecture, DV, firmware, and CAD teams across the full product lifecycle from concept through silicon validation and post-silicon debug.
• Apply agentic AI methodologies to scale and accelerate micro-architecture exploration and design execution.

Skills

FPGA micro-architecture

SystemVerilog/Verilog

SystemC/C++ models

Low-power design

Executive communication

Education

MS/PhD in Electrical or Computer Engineering

Tools

CAD tools

Job description

Lattice Semiconductor Corp. in San Jose, CA seeks a Principal FPGA Micro-Architect to define micro-architecture of fabric primitives and drive PPAU optimization across device families, targeting AI, robotics, data centers, and edge applications.

The ideal candidate has 15+ years of FPGA fabric experience, strong SystemVerilog/Verilog and SystemC/C++ modeling skills, and a proven track record from architecture through silicon validation.