Senior System Power Architect – Low-Power FPGA & SoC

Lattice Semiconductor Corp.; San Jose (CA); On-site; USD 198,000 - 242,000; Full time

Job summary

Lattice Semiconductor Corp. in San Jose, CA seeks a Senior System Power Architect to drive power analysis and low-power optimization for FPGA hardware and software.

You will design low-power feature specifications, algorithms, and collaborate with hardware, software, marketing, and applications teams. Candidates should have a BS/MS/PhD in EE/CE/CS with 6–8+ years of experience, strong RTL/power analysis, and hands-on with PrimePower/PrimeTime/SpyGlass/Joules/Voltus/PowerArtist, plus C/C++ and

Qualifications

• BS/MS/PhD in EE, CE, CS or related field with 8+/6+/3+ years of relevant experience.
• Strong knowledge of low-power design techniques and RTL/power analysis.
• Hands-on with industry power/timing tools (PrimePower, PrimeTime, SpyGlass, Joules, Voltus, PowerArtist) and proficiency in C/C++ and Python.

Responsibilities

• Define low-power feature specifications, user flows, and algorithms for software, marketing, and applications teams.
• Drive power-performance analysis to influence hardware/software roadmaps.
• Develop chip-level power estimation models for dynamic/static/clock/memory/I/O; correlate with simulations/silicon.
• Establish power-aware RTL methodology and power-aware synthesis flows.
• Develop power and competitive benchmarks.
• Lead and mentor junior engineers across distributed teams.

Skills

RTL design

Power analysis

C/C++

Python

Cross-functional

Power-aware synthesis

Education

BS in EE/CE/CS

MS in EE/CE/CS

PhD in EE/CE/CS

Tools

PrimePower

PrimeTime

SpyGlass

Joules

Voltus

PowerArtist

Job description

Lattice Semiconductor Corp. in San Jose, CA seeks a Senior System Power Architect to drive power analysis and low-power optimization for FPGA hardware and software.

You will design low-power feature specifications, algorithms, and collaborate with hardware, software, marketing, and applications teams. Candidates should have a BS/MS/PhD in EE/CE/CS with 6–8+ years of experience, strong RTL/power analysis, and hands-on with PrimePower/PrimeTime/SpyGlass/Joules/Voltus/PowerArtist, plus C/C++ and