Senior IP/FPGA Integration Architect

Lattice Semiconductor Corp; United States; On-site; USD 199,000 - 243,000; Full time

Benefits offered by this job

Healthcare benefits

Retirement plans

Paid time off

Job summary

Lattice Semiconductor Corp is seeking an experienced FPGA/ASIC design engineer to integrate IP blocks, manage sector-level constraints, and run complete sign-off cycles across RTL, synthesis, STA, and DFT flows. You will collaborate with IP, Product Engineering, and Test teams to incorporate power data into full-chip models and validate power assumptions.

Requires 15+ years in ASIC/SoC/FPGA design, and strong expertise in Verilog/SystemVerilog, RTL, and Cadence Virtuoso.

Qualifications

• BS or MS in Electronics/Computer/Electrical Engineering.
• 15+ years of experience in ASIC, SoC, or FPGA design and product development.
• Expertise in Verilog and SystemVerilog is a must.

Responsibilities

• Integrate IP blocks into FPGA platforms, delivering models and sign-off collateral.
• Create and maintain sector-level design constraints (SDC) and reconcile clock constraints.
• Run and maintain the digital implementation flow: RTL updates, synthesis, LEC, STA, DFT integration.
• Collaborate with IP Design, Product Engineering, and Test teams for power data integration.
• Run DV regressions and sign-off checks for sector releases and manage releases in version control.

Skills

Verilog

SystemVerilog

FPGA design

RTL

Scripting

Education

BS or MS in Electronics/Computer/Electrical Engineering

Tools

Cadence Virtuoso

Job description

Lattice Semiconductor Corp is seeking an experienced FPGA/ASIC design engineer to integrate IP blocks, manage sector-level constraints, and run complete sign-off cycles across RTL, synthesis, STA, and DFT flows. You will collaborate with IP, Product Engineering, and Test teams to incorporate power data into full-chip models and validate power assumptions.

Requires 15+ years in ASIC/SoC/FPGA design, and strong expertise in Verilog/SystemVerilog, RTL, and Cadence Virtuoso.