AI-Driven FPGA Architect — Power-Efficient Design

Lattice Semiconductor Corp

United States

On-site

USD 190,000 - 230,000

Full time

14 days+

A complete application in a minute

Tailored resume and cover letter, ready to send.

Get past ATS filters

Job summary

Lattice Semiconductor, “the low power programmable leader,” is seeking an experienced FPGA Architecture Engineer to define, evaluate, and realize next-generation FPGA architectures. This role connects architectural exploration with hardware implementation and software/CAD enablement, emphasizing power efficiency while balancing performance, area, and software quality of results.

You’ll collaborate with SW CAD development and IC HW design teams to ensure architecture meets SW QOR and HW PPA

Qualifications

  • BS, MS, or PhD in electrical engineering, computer engineering, computer science, or a related field.
  • Typically, 10 years of relevant experience; candidates with strong relevant accomplishments and fewer years will also be considered.
  • Experience in FPGA architecture, FPGA CAD, or ASIC/chip design, with demonstrated ability to reason about architectural tradeoffs.
  • Understanding of digital design and the relationship between architecture, implementation, and power, performance, and area.
  • Programming and modeling skills for architectural research and analysis, including Python; familiarity with Verilog or VHDL.
  • Initiative, clear technical communication, and effective cross-functional collaboration.
  • Especially Valuable: Experience with commercial FPGA architectures and CAD tools.
  • Experience connecting architectural decisions to hardware implementation, CAD behavior, or customer workloads.
  • Relevant FPGA architecture research supported by models, experiments, or publications.
  • Experience applying AI/ML or generative-AI tools to engineering problems, with an interest in advancing their practical use.

Responsibilities

  • Evaluate and define next generation FPGA fabric architectures
  • AI-accelerated FPGA architectural exploration and optimization
  • FPGA architectural modeling and evaluation
  • Work closely with SW CAD development and IC HW design teams to ensure the architecture can meet SW QOR (Quality of Results) and HW PPA (Power, Performance, Area) goals

Skills

FPGA architecture
FPGA CAD tools
Python
Verilog/VHDL

Education

BS, MS, or PhD in electrical engineering, computer engineering, computer science

Tools

FPGA CAD tools
ASIC/FPGA CAD tools

Job description

Lattice Semiconductor, “the low power programmable leader,” is seeking an experienced FPGA Architecture Engineer to define, evaluate, and realize next-generation FPGA architectures. This role connects architectural exploration with hardware implementation and software/CAD enablement, emphasizing power efficiency while balancing performance, area, and software quality of results.

You’ll collaborate with SW CAD development and IC HW design teams to ensure architecture meets SW QOR and HW PPA

Get your free, confidential resume review.

or drag and drop your file here.

Similar jobs

Similar jobs worth comparing

AI-Driven FPGA Architectures Engineer
AI-Driven FPGA Architectures Engineer

Lattice Semiconductor • San Jose (CA)

On-site
USD 180,000 - 223,000
FPGA Architecture Engineer — AI-Driven, Power-Efficient Design
FPGA Architecture Engineer — AI-Driven, Power-Efficient Design

Lattice Semiconductor Corp. • San Jose (CA), Northern (KY)

Hybrid
USD 171,000 - 232,000
FPGA Architecture Engineer
FPGA Architecture Engineer

Lattice Semiconductor Corp • United States

On-site
USD 190,000 - 230,000
FPGA Architecture Engineer
FPGA Architecture Engineer

Lattice Semiconductor • San Jose (CA)

On-site
USD 180,000 - 223,000
FPGA Architecture Engineer
FPGA Architecture Engineer

Lattice Semiconductor Corp. • San Jose (CA), Northern (KY)

Hybrid
USD 171,000 - 232,000
Principal CAD/EDA Architect — Design Automation & Infra
Principal CAD/EDA Architect — Design Automation & Infra

Lattice Semiconductor Corp • United States

On-site
USD 231,000 - 290,000
Equity
Healthcare
Retirement plans
+1
Senior IP/FPGA Integration Architect
Senior IP/FPGA Integration Architect

Lattice Semiconductor Corp • United States

On-site
USD 199,000 - 243,000
Healthcare benefits
Retirement plans
Paid time off
Lead Digital Design Engineer — Power-Efficient Edge SoC
Lead Digital Design Engineer — Power-Efficient Edge SoC

Efficient Computer • San Jose (CA)

On-site
USD 160,000 - 270,000
401K match
Equity program
Paid parental leave
+1
Senior Staff FPGA & IP Integration Engineer
Senior Staff FPGA & IP Integration Engineer

Lattice Semiconductor Corp. • San Jose (CA), Northern (KY)

Hybrid
USD 221,000 - 320,000
Healthcare and retirement plans
Equity
Paid time off
Senior Memory Architect: High-Speed, Low-Power RAM Design
Senior Memory Architect: High-Speed, Low-Power RAM Design

Lattice Semiconductor • San Jose (CA)

On-site
USD 221,000 - 260,000
Healthcare
Retirement plans
Paid time off