Principal FPGA Micro-Architect

Lattice Semiconductor Corp.; San Jose (CA); In loco; USD 225.000 - 275.000; Tempo pieno

Descrizione del lavoro

Lattice Semiconductor Corp. in San Jose, CA seeks a Principal FPGA Micro-Architect to define micro-architecture of fabric primitives and drive PPAU optimization across device families, targeting AI, robotics, data centers, and edge applications.

The ideal candidate has 15+ years of FPGA fabric experience, strong SystemVerilog/Verilog and SystemC/C++ modeling skills, and a proven track record from architecture through silicon validation.

Competenze

• MS/PhD in Electrical or Computer Engineering with 15+ years of FPGA fabric micro-architecture experience.
• Proven track record delivering FPGA primitives from architecture through tape-out.
• Deep expertise in logic elements, DSP blocks, embedded memory, interconnect routing muxes, carry chains, and clocking structures.
• Proficiency in SystemVerilog/Verilog and SystemC/C++ architectural modeling for performance analysis and design trade-off evaluation.
• Extensive hands-on experience in silicon validation and post-silicon debug of FPGA fabric blocks, including bring-up and root-cause analysis.

Mansioni

• Define micro-architecture of core fabric primitives: programmable logic elements, DSP blocks, embedded memory blocks, interconnect routing, configuration memory, carry chains, and clocking structures.
• Drive fabric PPAU optimization across device generations; evaluate implementation and routing feasibility and drive design trade-offs for modularity and scalability.
• Develop SystemC/C++ architectural models to drive performance analysis and evaluate fabric design trade-offs ahead of RTL/schematic availability.
• Lead advanced low-power fabric design including clock and power islands, power gating, dual-rail architectures, and dynamic power mode switching.
• Drive software primitive definition and implementation strategy, ensuring fabric elements are mapped to CAD tools and customer design flows for maximum usability.
• Partner with architecture, DV, firmware, and CAD teams across the full product lifecycle from concept through silicon validation and post-silicon debug.
• Apply agentic AI methodologies to scale and accelerate micro-architecture exploration and design execution.

Conoscenze

FPGA micro-architecture

SystemVerilog/Verilog

SystemC/C++ models

Low-power design

Executive communication

Formazione

MS/PhD in Electrical or Computer Engineering

Strumenti

CAD tools

Descrizione del lavoro

# Join the FPGA Leader## Principal FPGA Micro-ArchitectApply: San Jose, CA: Full time: Posted Yesterday: R-103539# **Lattice Overview**There is energy here...energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.**Job Description:**We are seeking a **Principal FPGA Micro-Architect** with deep expertise in programmable logic fabric design and a track record of delivering next-generation FPGA devices from concept to silicon. You will define and drive the micro-architecture of Lattice's FPGA fabric primitives, optimizing for power, performance, area, and utilization across device families. You will shape the architecture of next-generation FPGAs targeting Physical AI, Robotics, Space, Data Centers, and edge applications — markets where Lattice's low-power leadership is a decisive advantage.**Key Responsibilities** · Define micro-architecture of core fabric primitives: Programmable Logic Elements, DSP blocks, embedded memory blocks, interconnect routing, configuration memory, carry chains, and clocking structures· Drive fabric PPAU (power, performance, area, and utilization) optimization; evaluate implementation and routing feasibility and drive design trade-offs for modularity and scalability across device generations· Develop SystemC/C++ architectural models to drive performance analysis and evaluate fabric design trade-offs ahead of RTL/schematic availability· Lead advanced low-power fabric design including clock and power islands, power gating, dual-rail architectures, and dynamic power mode switching· Drive software primitive definition and implementation strategy, ensuring fabric elements are optimally mapped to CAD tools and customer design flows for maximum usability· Partner with architecture, DV, firmware, and CAD teams across the full product lifecycle from concept through silicon validation and post-silicon debug· Apply agentic AI methodologies to scale and accelerate micro-architecture exploration and design execution**Required Qualifications** · MS/PhD in Electrical or Computer Engineering with 15+ years of FPGA fabric micro-architecture experience· Established track record of delivering FPGA fabric primitives from architecture definition through tape-out and silicon validation, with demonstrated ability to define software primitives and drive implementation strategy for optimal fabric usability in customer design flows· Deep expertise in FPGA fabric elements including logic elements, DSP blocks, embedded memory blocks, interconnect routing muxes, carry chains, and clocking structures· Proficiency in SystemVerilog/Verilog and SystemC/C++ architectural modeling for performance analysis and design trade-off evaluation· Deep experience in advanced low-power design: clock and power islands, power gating, multi-rail, and dynamic power mode switching· Extensive hands-on experience in silicon validation and post-silicon debug of FPGA fabric blocks, including bring-up, characterization, and root-cause analysis of fabric-level sightings· Strong written and oral communication skills with a history of executive-level presentations **Pay & Benefits**Consistent with Lattice Semiconductor values and applicable law, we provide the following information to promote pay transparency and equity. We have a market-based pay structure which varies by location. Please note that the base pay range is a guideline, and our compensation range reflects the cost of labor in the U.S. geographic market based on the location of the role. Pay within these ranges varies and depends on job-related knowledge, skills, and relevant work experience.For candidates who receive and offer, the starting salary will vary based on various factors including, but not limited to, such qualifications as, skill level, competencies, and work location. The range provided may represent a candidate range and may not reflect the full range for an individual tenured employee.**Base Pay Range**250,000.00In addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity. In addition, this role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more!**Additional Information:**This position requires a successful background and reference checks and satisfactory proof of your right to work in the United States.Lattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry. Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. Lattice is an international, service-driven developer of innovative low cost, low power programmable design solutions. Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win. For more information about how our FPGA, CPLD and programmable power management devices help our customers unlock their innovation, visit www.latticesemi.com. You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace. Applications are welcome from all qualified candidates. As an E-Verify employer, we use this system to confirm the employment eligibility of all new hires in accordance with federal law. All applicants will be required to complete a Form I-9, Employment Eligibility Verification, upon hire. We do not use E-Verify to pre-screen job candidates and will comply with all E-Verify regulations.