Senior FPGA Design Architect – RTL, DDR, RISC-V

Lattice Semiconductor Corp.; San Jose (CA); On-site; USD 150,000 - 230,000; Full time

Job summary

Lattice Semiconductor Corp. is seeking a Sr. Staff Design Engineer in San Jose, CA. You will drive RTL design and verification, build embedded systems in Lattice FPGAs, and integrate IPs into FPGA software flows, collaborating across software and applications teams to meet customer needs.

The role emphasizes architecting soft IPs, optimizing performance, and leading development efforts for high-speed interfaces and RISC-V based designs. Strong debugging and timing closure skills are essential.

Qualifications

• Bachelor’s degree in Electronics Engineering, Applied Physics or related field.
• 8+ years of experience in FPGA/SoC design and related IP work.
• Experience with DDR protocols (DDR3/4/LPDDR4/5) and high-speed interfaces (PCIe, Ethernet, MIPI).
• Proficiency in RTL design, verification, debugging and timing closure.

Responsibilities

• Architect and develop DDR Memory Controller soft IPs.
• Optimize IPs for latency, size and frequency.
• Design and implement FPGA RTL and software primitives.
• Integrate with third-party hardened PHYs and verify hardware interoperability.
• Lead cross-functional teams and coordinate development efforts.
• Perform STA and constraint writing; support customer solutions.

Skills

FPGA RTL design

SoC/ASIC development

High-speed interfaces

IP for FPGA/ASIC

RISC-V system design

Debug & timing closure

Hardware validation

Team leadership

Education

Bachelor’s degree in Electronics Engineering or related field

Job description

Lattice Semiconductor Corp. is seeking a Sr. Staff Design Engineer in San Jose, CA. You will drive RTL design and verification, build embedded systems in Lattice FPGAs, and integrate IPs into FPGA software flows, collaborating across software and applications teams to meet customer needs.

The role emphasizes architecting soft IPs, optimizing performance, and leading development efforts for high-speed interfaces and RISC-V based designs. Strong debugging and timing closure skills are essential.