Senior System Power Architect - Low-Power FPGA Leader

Lattice Semiconductor Corp; United States; On-site; USD 198,000 - 242,000; Full time

Benefits offered by this job

Equity

Variable compensation

Healthcare benefits

Retirement plans

Paid time off

Job summary

Lattice Semiconductor Corp in the United States is seeking a Senior System Power Architect to drive power analysis and low-power optimization across FPGA hardware and software. You will design feature specs, methodologies, and work with hardware, software, marketing, and applications teams.

The role requires strong RTL and gate-level power analysis, experience with industry tools, and proficiency in C/C++ and Python.

Qualifications

• BS/MS/PhD in EE, CE, CS or related field with 8+/6+/3+ years of experience.
• Strong knowledge of low-power design techniques.
• Deep expertise in RTL and gate-level power analysis and optimization.

Responsibilities

• Define low-power feature specifications, user flows, algorithms, and align software, marketing, and applications teams.
• Drive power-performance analysis to influence hardware and software roadmaps.
• Develop chip-level power estimation models covering dynamic, static, clock, memory, and I/O, and correlate models with simulations and silicon.
• Establish power-aware RTL methodology.
• Develop power and competitive benchmarks.
• Lead and mentor junior engineers across distributed teams.

Skills

Low-power design techniques

RTL power analysis

Power-aware synthesis & P&R

C/C++

Python

Cross-functional alignment

Strong communication

FPGA architecture knowledge

Education

BS in EE/CE/CS

MS in EE/CE/CS

PhD in related field

Tools

PrimePower

PrimeTime

SpyGlass

Joules

Voltus

PowerArtist

Job description

Lattice Semiconductor Corp in the United States is seeking a Senior System Power Architect to drive power analysis and low-power optimization across FPGA hardware and software. You will design feature specs, methodologies, and work with hardware, software, marketing, and applications teams.

The role requires strong RTL and gate-level power analysis, experience with industry tools, and proficiency in C/C++ and Python.