Senior FPGA Power Architect – Low-Power Design

Lattice Semiconductor; San Jose (CA); Sur place; USD 198 000 - 242 000; Plein temps

Résumé du poste

Lattice Semiconductor is seeking a Senior System Power Architect to lead power analysis and low‑power optimization across FPGA hardware and software. You will define feature specifications and collaborate with hardware, software, marketing, and applications teams.

Responsibilities include developing chip‑level power estimation models, establishing power‑aware RTL methodology, and driving power‑performance analysis to influence roadmaps.

Qualifications

• BS/MS/PhD in EE, CE, CS, or related field.
• Strong knowledge of low-power design techniques.
• Deep expertise in RTL and gate-level power analysis and optimization, plus power-aware synthesis and P&R.
• Hands-on experience with industry power/timing tools (PrimePower, PrimeTime, SpyGlass, Joules, Voltus, PowerArtist) and STA.
• Proficiency in C/C++ and Python.
• Strong written and verbal communication skills.
• Ability to drive cross-functional alignment.
• Knowledge of FPGA architecture and design flows is strongly preferred.

Responsabilités

• Define low-power feature specifications, user flows, algorithms, and align software, marketing, and applications teams
• Drive power-performance analysis to influence hardware and software roadmaps
• Develop chip-level power estimation models covering dynamic, static, clock, memory, and I/O, and correlate models with simulations and silicon
• Establish power-aware RTL methodology
• Develop power and competitive benchmarks
• Lead and mentor junior engineers across distributed teams

Connaissances

Low-power design

RTL power analysis

Power-aware synthesis

C/C++

Python

Communication skills

Cross-functional alignment

FPGA architecture knowledge

Formation

BS/MS/PhD in EE, CE, CS, or related field

Outils

PrimePower

PrimeTime

SpyGlass

Joules

Voltus

PowerArtist

Description du poste

Lattice Semiconductor is seeking a Senior System Power Architect to lead power analysis and low‑power optimization across FPGA hardware and software. You will define feature specifications and collaborate with hardware, software, marketing, and applications teams.

Responsibilities include developing chip‑level power estimation models, establishing power‑aware RTL methodology, and driving power‑performance analysis to influence roadmaps.