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GCS Recruitment is seeking a Senior FPGA Engineer to lead RTL design for advanced satellite payload hardware. You will build FPGA logic in Verilog/SystemVerilog or VHDL and integrate high‑speed interfaces such as PCIe, JESD204, Aurora and Ethernet. You will own timing closure and perform hardware bring‑up in a lab environment.
The role requires hands‑on debugging, board bring‑up, and close collaboration with electrical, hardware, and systems teams to deliver validated FPGA solutions.
GCS Recruitment is seeking a Senior FPGA Engineer to lead RTL design for advanced satellite payload hardware. You will build FPGA logic in Verilog/SystemVerilog or VHDL and integrate high‑speed interfaces such as PCIe, JESD204, Aurora and Ethernet. You will own timing closure and perform hardware bring‑up in a lab environment.
The role requires hands‑on debugging, board bring‑up, and close collaboration with electrical, hardware, and systems teams to deliver validated FPGA solutions.