Senior FPGA Engineer: Verilog RTL, Versal & Timing

GCS Recruitment; Kent (WA); Vor Ort; USD 120.000 - 160.000; Vollzeit

Zusammenfassung

GCS Recruitment seeks an experienced FPGA Engineer to design and deliver high-performance FPGA solutions for a satellite communication system. You will collaborate with system architects and cross-functional teams to define, implement, validate, and release FPGA-based networking functions.

You will lead the full FPGA lifecycle, from architecture through production release, including synthesis, place-and-route, timing closure, and testbench development.

Qualifikationen

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related technical field.
• 7+ years of hands-on FPGA design experience.
• Strong expertise with Verilog HDL for RTL design and verification.
• Experience designing with AMD Xilinx Versal ACAP FPGA architecture.
• Experience working with Microchip IGLOO2 FPGA platforms.
• Proficiency with FPGA development tools such as Xilinx Vivado and Microchip Libero SoC.
• Experience with simulation tools such as ModelSim, Vivado Simulator, VCS (or equivalent).
• Experience using scripting languages such as Python, TCL, or Perl for design automation.
• Background in digital communications, networking, or signal processing.
• Experience with DO-254 or other safety-critical design standards.

Aufgaben

• Own the development and delivery of one or more FPGA bitstreams.
• Design, develop, and implement complex FPGA architectures using Verilog HDL.
• Lead FPGA development across the complete lifecycle, including RTL Design, Timing Closure, and Production Release.
• Develop FPGA-based networking and digital communication functions.
• Collaborate with system architects and cross-functional teams to validate FPGA solutions.
• Build FPGA prototypes to evaluate architecture and design tradeoffs.
• Support hardware bring-up, system integration, and debugging involving FPGA, RF, firmware, and networking components.
• Perform synthesis, place & route, timing analysis, and design optimization.
• Develop thorough testbenches and simulation environments.
• Debug FPGA designs in simulation and hardware environments.
• Create design specifications and verification plans.

Kenntnisse

Verilog HDL

SystemVerilog

RTL Design

Timing Closure

CDC Analysis

Python scripting

Ausbildung

Bachelor's degree in Electrical Engineering or related

Tools

Xilinx Vivado

Libero SoC

ModelSim

Vivado Simulator

VCS

Git

SVN

Jobbeschreibung

GCS Recruitment seeks an experienced FPGA Engineer to design and deliver high-performance FPGA solutions for a satellite communication system. You will collaborate with system architects and cross-functional teams to define, implement, validate, and release FPGA-based networking functions.

You will lead the full FPGA lifecycle, from architecture through production release, including synthesis, place-and-route, timing closure, and testbench development.