Senior FPGA Engineer: Satellite Networking & HDL Lead

GCS Recruitment; Beaverton (OR); On-site; USD 130,000 - 190,000; Full time

Job summary

GCS Recruitment partners with a leading aerospace/communications org to hire a Senior FPGA Engineer in Beaverton, Oregon. You will design and deliver advanced FPGA solutions for a next‑gen satellite communication system, collaborating with system architects and cross‑functional teams.

You will own FPGA bitstreams, develop with Verilog/SystemVerilog, perform timing closure, validation, and production release, and help with hardware bring‑up, tests, and documentation.

Qualifications

• 7+ years of hands-on FPGA design experience.
• Strong expertise with Verilog HDL for RTL design and verification.
• Experience designing with AMD Xilinx Versal ACAP and Microchip IGLOO2.
• Proficiency with FPGA development tools (Vivado, Libero SoC).
• Ability to work with system architects and cross-functional teams.

Responsibilities

• Own the development and delivery of one or more FPGA bitstreams.
• Design, develop, and implement complex FPGA architectures using Verilog HDL.
• Lead FPGA development across the complete lifecycle: microarchitecture, RTL design, timing closure.
• Perform synthesis, place & route, timing analysis, and design optimization.
• Develop testbenches, simulate, and validate FPGA designs in hardware and lab.
• Collaborate with hardware, firmware, and software teams to validate FPGA solutions.
• Support manufacturing, production deployment, and post-release engineering activities.

Skills

Verilog HDL

SystemVerilog

Python

TCL

Perl

Problem solving

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field

Tools

Xilinx Vivado

Libero SoC

ModelSim

Vivado Simulator

VCS

Git

SVN

Job description

GCS Recruitment partners with a leading aerospace/communications org to hire a Senior FPGA Engineer in Beaverton, Oregon. You will design and deliver advanced FPGA solutions for a next‑gen satellite communication system, collaborating with system architects and cross‑functional teams.

You will own FPGA bitstreams, develop with Verilog/SystemVerilog, perform timing closure, validation, and production release, and help with hardware bring‑up, tests, and documentation.