Senior FPGA Engineer (Phased-Array Satellite Links)

GCS Recruitment; San Francisco (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

GCS Recruitment is seeking an FPGA Engineer to help develop next-generation phased-array payload electronics for LEO connectivity. You will design RTL and FPGA-based data paths, integrate high-speed interfaces, and work across hardware teams to bring up and validate new platforms.

The role combines hands-on hardware testing with design verification, timing closure, and documentation to ensure reliable performance in fast-paced satellite hardware environments.

Qualifications

• Experience designing RTL for data movement, control and monitoring within DSP/data paths.
• Proven FPGA development experience for high-speed interfaces.
• Hands-on debugging, JTAG and logic analyzer usage in hardware bring-up.
• Familiarity with lab testing and validation of complex FPGA-based systems.

Responsibilities

• Design, develop, and integrate FPGA-based solutions for phased-array communication systems.
• Create RTL for data movement, control, monitoring, and integration within the digital signal chain.
• Implement and validate high-speed FPGA interfaces, including multi-gigabit SerDes and JESD-class links.
• Perform timing closure, constraints development, optimization, and build management for reliable hardware performance.
• Support FPGA bring-up, debugging, and validation on new hardware platforms.
• Collaborate with hardware engineers to troubleshoot system-level issues using JTAG and lab equipment.
• Develop diagnostic and monitoring capabilities, including error detection and status reporting.
• Participate in system integration, testing, and validation activities.

Skills

RTL design

FPGA development

JTAG

Hardware debugging

Tools

SerDes

Lab test equipment

Job description

GCS Recruitment is seeking an FPGA Engineer to help develop next-generation phased-array payload electronics for LEO connectivity. You will design RTL and FPGA-based data paths, integrate high-speed interfaces, and work across hardware teams to bring up and validate new platforms.

The role combines hands-on hardware testing with design verification, timing closure, and documentation to ensure reliable performance in fast-paced satellite hardware environments.