Senior FPGA Engineer - RTL, Timing Closure (Hybrid)

Actalent; Newtown (PA); Hybrid; USD 76,000 - 92,000; Full time

Benefits offered by this job

Medical benefits

Dental & Vision

401(k) plan

Life Insurance

Disability

HSA

Transportation support

EAP

Paid time off

Job summary

Actalent seeks an experienced FPGA Engineer to drive RTL design, FPGA development and verification for production-ready FPGA-based products. You will collaborate with hardware, embedded software and test teams to ensure robust designs and timely deployments.

The role emphasizes high-speed timing closure, extensive RTL coding in VHDL (Verilog accepted), and hands-on debugging in a collaborative lab environment. Hybrid work in Newtown, PA is offered.

Qualifications

• 7-10 years of FPGA experience with RTL design.
• Focus on FPGA development, simulation, verification and timing closure.
• Collaborate with hardware, embedded software and test engineers.
• Provide product development support and lab debugging.

Responsibilities

• Design and develop FPGA-based products with RTL design, FPGA development and simulation.
• Collaborate with hardware, embedded software and test engineers to enable product development.
• Perform simulation and verification to validate designs before deployment.
• Achieve timing closure on high-speed FPGA designs via timing analysis and optimization.
• Provide product development support and assist in lab debugging and troubleshooting.

Skills

RTL coding (VHDL)

RTL coding (Verilog)

FPGA development

Simulation & verification

Timing analysis

Xilinx FPGA experience

Python scripting

TCL scripting

Lab debugging

Cross-functional collaboration

Intel/Altera experience

Job description

Actalent seeks an experienced FPGA Engineer to drive RTL design, FPGA development and verification for production-ready FPGA-based products. You will collaborate with hardware, embedded software and test teams to ensure robust designs and timely deployments.

The role emphasizes high-speed timing closure, extensive RTL coding in VHDL (Verilog accepted), and hands-on debugging in a collaborative lab environment. Hybrid work in Newtown, PA is offered.