Senior FPGA Design Engineer - Onsite, 9/80

Actalent; Greenville (SC); On-site; USD 103,000 - 124,000; Full time

Benefits offered by this job

Medical, dental & vision

401(k) Retirement Plan

Life Insurance

Job summary

Actalent in Greenville, SC is seeking a Senior FPGA Design Engineer with 8+ years of experience to lead the development, verification, and integration of high-speed FPGA solutions across PCIe Gen4/5, 10–100G Ethernet, and DDR4/DDR5.

You will design RTL in Verilog/VHDL/SystemVerilog, build robust testbenches, perform timing and power analysis, and mentor junior engineers, while working onsite in a diverse team dedicated to reliability and performance.

Qualifications

• 8+ years of FPGA design experience.
• RTL design using Verilog/VHDL/SystemVerilog and testbench development.
• Experience with PCIe Gen4/5, 10–100G Ethernet, and DDR4/DDR5.
• Ability to lead full lifecycle FPGA development and mentor juniors.
• Familiarity with DFT features (JTAG) and design-for-test standards.
• Secret clearance or ability to obtain it.

Responsibilities

• Lead full life-cycle FPGA development from requirements to system integration.
• Define FPGA architecture with diagrams, clocking strategies, and reviews.
• Develop robust testbenches and achieve code coverage closure.
• Create detailed test plans, procedures, and verifications.
• Collaborate with hardware/software teams for board/system integration.
• Implement JTAG boundary scan and other DFT features.
• Mentor junior engineers and drive design-practice improvements.

Skills

RTL design Verilog/VHDL

Testbench development

Vivado

Quartus

High-speed interfaces

SoC integration

JTAG/DFT

Secret Clearance

FPGA Block Design

UVM familiarity

Version control scripting

Lab validation

Agile collaboration

Formal verification

Tools

Xilinx Vivado

Intel Quartus

Job description

Actalent in Greenville, SC is seeking a Senior FPGA Design Engineer with 8+ years of experience to lead the development, verification, and integration of high-speed FPGA solutions across PCIe Gen4/5, 10–100G Ethernet, and DDR4/DDR5.

You will design RTL in Verilog/VHDL/SystemVerilog, build robust testbenches, perform timing and power analysis, and mentor junior engineers, while working onsite in a diverse team dedicated to reliability and performance.