Principal RTL Design Engineer - Hybrid

Cypress HCM; San Francisco (CA); Hybrid; USD 180,000 - 240,000; Full time

Benefits offered by this job

Medical benefits

401K with company match

Employee stock purchase plan

ESOP discount

Job summary

Cypress HCM is seeking an experienced RTL design lead for ASIC/FPGA developments in a hybrid San Jose, CA Hillsboro, OR area. You will drive architecture decisions, mentor teams, and collaborate across verification, implementation, and customer engagements.

The role requires 8+ years of logic design, expertise in Verilog/SystemVerilog and UVM, and strong memories/interfaces knowledge. A BSEE or MSEE is preferred, with competitive benefits and stock options.

Qualifications

• 8+ years of logic design experience in ASIC/FPGA development.
• Proficiency in Verilog/SystemVerilog RTL design and UVM-based verification environments.
• Background in high-speed memory or interface technologies.

Responsibilities

• Lead RTL design and microarchitecture development for complex digital logic blocks.
• Drive architecture decisions through performance, power, and area analysis.
• Partner with verification teams to improve test strategies and coverage.
• Collaborate with implementation teams to resolve design timing and power challenges.
• Debug and resolve design issues identified during verification and validation.
• Support technical discussions during customer evaluations and engagements.
• Assist with product integration and deployment activities.

Skills

RTL design

SystemVerilog

Verilog

UVM verification

Performance analysis

Timing closure

Python scripting

TCL scripting

Memory interfaces

Collaboration & leadership

Education

BSEE

MSEE

Tools

Questas

Incisive

VCS

Verilog

SystemVerilog

Python

TCL

Job description

Cypress HCM is seeking an experienced RTL design lead for ASIC/FPGA developments in a hybrid San Jose, CA Hillsboro, OR area. You will drive architecture decisions, mentor teams, and collaborate across verification, implementation, and customer engagements.

The role requires 8+ years of logic design, expertise in Verilog/SystemVerilog and UVM, and strong memories/interfaces knowledge. A BSEE or MSEE is preferred, with competitive benefits and stock options.