Senior FPGA Design & Verification Engineer

RiseMe; Arizona; On-site; USD 108,000 - 162,000; Full time

Job summary

Northrop Grumman Space Systems in Chandler, AZ is seeking a Principal FPGA Digital Engineer to support the EO Group within Launch Vehicles. You will develop and test FPGA designs with hardware, algorithms, and software teams to address complex integration challenges.

The role requires hands-on verification of timing and functionality, creation of test benches, and ongoing design documentation. You’ll leverage Vivado/Vitis, OSVVM/UVM, and FPGA resources to deliver robust solutions.

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related discipline with 5+ years of experience
• Ability to obtain a U.S. Government DoD Secret security clearance at time of application
• Solid FPGA/SoC design background with VHDL/Verilog
• Experience with AMD Xilinx FPGAs/SoCs
• Timing analysis with Vivado IDE
• Experience with MOSA interfaces/buses (Ethernet, PCIe, AXI4, UART)
• OSVVM or UVM knowledge; OSVVM preferred

Responsibilities

• Collaborate with multidisciplinary teams to resolve design challenges
• Develop and execute test benches to verify timing and functionality
• Generate, verify & integrate IO and image processing HDL modules
• Ensure compliance with internal design standards throughout development
• Oversee multiple FPGA bitstream configurations for varied use cases
• Prepare and maintain design documentation and verification reports
• Stay current with evolving FPGA technologies and tools

Skills

FPGA/SoC design

VHDL

Verilog

Vivado IDE

Vitis Unified IDE

OSVVM

UVM

Questa/ModelSim

DDR memory interfaces

AXI/PCIe/Ethernet

Embedded C/C++

Education

Bachelor’s degree in Electrical/Computer Engineering or related field

Master’s degree

PhD

Tools

Vivado IDE

Vitis IDE

Questa

ModelSim

Job description

Northrop Grumman Space Systems in Chandler, AZ is seeking a Principal FPGA Digital Engineer to support the EO Group within Launch Vehicles. You will develop and test FPGA designs with hardware, algorithms, and software teams to address complex integration challenges.

The role requires hands-on verification of timing and functionality, creation of test benches, and ongoing design documentation. You’ll leverage Vivado/Vitis, OSVVM/UVM, and FPGA resources to deliver robust solutions.