Principal FPGA Digital Engineer — Secret Clearance

Northrop Grumman; United States; On-site; USD 108,000 - 162,000; Full time

Benefits offered by this job

Relocation assistance may be available

Job summary

Northrop Grumman Space Systems is seeking a Principal FPGA Digital Engineer in Chandler, AZ to drive flagship FPGA design efforts for EO systems. You will develop test benches, validate timing and functionality, and work with hardware, algorithms, and software teams to deliver integrated hardware solutions.

The role requires current DoD Secret eligibility, strong VHDL/Verilog expertise, and hands-on experience with Xilinx FPGAs and Vivado.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related discipline with 5+ years experience; or advanced degree with less experience.
• Ability to obtain DoD Secret clearance at application time.
• Strong background in FPGA/SoC design with VHDL/Verilog.
• Experience with AMD Xilinx FPGAs/SoCs.
• Experience in timing analysis and Vivado IDE for target performance.
• Proficiency with MOSA/UVM verification methodologies (OSVVM preferred).

Responsibilities

• Collaborate with senior FPGA engineers and cross‑disciplinary teams to resolve design and integration challenges.
• Develop and execute advanced test benches to verify functional and timing requirements.
• Generate, verify & integrate IO and image processing HDL modules within the device architecture.
• Ensure compliance with internal design standards across the lifecycle.
• Manage multiple FPGA bitstream configurations for varied use cases.
• Prepare, present, and maintain design documentation including schematics and verification reports.
• Stay updated on evolving FPGA technologies, tools, and methodologies.

Skills

FPGA/SoC design

VHDL/Verilog

AMD Xilinx FPGAs

Vivado IDE

OSVVM/UVM

Timing constraints

MOSA interfaces

Debugging tools

Education

Bachelor's degree in Electrical Engineering

Master's or PhD (preferred)

Tools

Questa/ModelSim

Job description

Northrop Grumman Space Systems is seeking a Principal FPGA Digital Engineer in Chandler, AZ to drive flagship FPGA design efforts for EO systems. You will develop test benches, validate timing and functionality, and work with hardware, algorithms, and software teams to deliver integrated hardware solutions.

The role requires current DoD Secret eligibility, strong VHDL/Verilog expertise, and hands-on experience with Xilinx FPGAs and Vivado.