Principal FPGA Digital Engineer - 3

Northrop Grumman; United States; On-site; USD 108,000 - 162,000; Full time

Benefits offered by this job

Relocation assistance may be available

Job summary

Northrop Grumman Space Systems is seeking a Principal FPGA Digital Engineer in Chandler, AZ to drive flagship FPGA design efforts for EO systems. You will develop test benches, validate timing and functionality, and work with hardware, algorithms, and software teams to deliver integrated hardware solutions.

The role requires current DoD Secret eligibility, strong VHDL/Verilog expertise, and hands-on experience with Xilinx FPGAs and Vivado.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related discipline with 5+ years experience; or advanced degree with less experience.
• Ability to obtain DoD Secret clearance at application time.
• Strong background in FPGA/SoC design with VHDL/Verilog.
• Experience with AMD Xilinx FPGAs/SoCs.
• Experience in timing analysis and Vivado IDE for target performance.
• Proficiency with MOSA/UVM verification methodologies (OSVVM preferred).

Responsibilities

• Collaborate with senior FPGA engineers and cross‑disciplinary teams to resolve design and integration challenges.
• Develop and execute advanced test benches to verify functional and timing requirements.
• Generate, verify & integrate IO and image processing HDL modules within the device architecture.
• Ensure compliance with internal design standards across the lifecycle.
• Manage multiple FPGA bitstream configurations for varied use cases.
• Prepare, present, and maintain design documentation including schematics and verification reports.
• Stay updated on evolving FPGA technologies, tools, and methodologies.

Skills

FPGA/SoC design

VHDL/Verilog

AMD Xilinx FPGAs

Vivado IDE

OSVVM/UVM

Timing constraints

MOSA interfaces

Debugging tools

Education

Bachelor's degree in Electrical Engineering

Master's or PhD (preferred)

Tools

Questa/ModelSim

Job description

RELOCATION ASSISTANCE: Relocation assistance may be available

CLEARANCE REQUIRED FOR START: Yes

CLEARANCE TYPE: Secret

TRAVEL: Yes, 10% of the Time Description

At Northrop Grumman, our employees have incredible opportunities to work on revolutionary systems that impact people's lives around the world today, and for generations to come. Our pioneering and inventive spirit has enabled us to be at the forefront of many technological advancements in our nation's history - from the first flight across the Atlantic Ocean, to stealth bombers, to landing on the moon. We look for people who have bold new ideas, courage and a pioneering spirit to join forces to invent the future, and have fun along the way. Our culture thrives on intellectual curiosity, cognitive diversity and bringing your whole self to work - and we have an insatiable drive to do what others think is impossible. Our employees are not only part of history, they're making history.

Northrop Grumman Space Systems is looking for a Principal FPGA Digital Engineer to support the Electro-Optics (EO) Group within the Launch Vehicles business unit in Chandler, Arizona.

As a principal FPGA design engineer, you will work closely with senior FPGA engineers and cross‑disciplinary teams (hardware, algorithms, and software) to address design challenges and ensure seamless hardware integration. This role will focus on developing and executing test benches to independently validate FPGA designs for functional correctness and timing requirements, while adhering to internal design standards. The ideal candidate excels in fast‑paced, collaborative environments and is comfortable managing multiple diverse assignments.

Responsibilities

• Collaborate with senior FPGA engineers and multidisciplinary teams (hardware, algorithms, software) to resolve design and integration challenges
• Develop and execute advanced test benches to verify that FPGA designs meet functional and timing requirements
• Generate, verify & integrate IO and image processing HDL modules. including functions definitions, HDL coding, module level sim and integration with overall device architecture
• Ensure compliance with internal design standards throughout the development lifecycle
• Oversee configuration management of multiple FPGA bitstream build configurations to support varied use cases or platform requirements
• Prepare, present, and maintain comprehensive design documentation, including schematics, simulation results, and verification reports
• Continuously expand technical knowledge by staying abreast of evolving FPGA technologies, tools, and industry methodologies

Basic Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related discipline from an accredited university and 5 years of relevant experience; or a Master's degree and 3 years of experience; or a PhD and 1 year of experience.
• Ability to obtain a U.S. Government Department of Defense (DoD) Secret security clearance at the time of application.
• Solid background in FPGA/SoC design, including complex firmware development using VHDL (preferred) or Verilog.
• Significant experience with AMD Xilinx FPGAs and SoCs.
• Knowledgeable in managing design constraints (timing, power, I/O) and performing static timing analysis to achieve critical performance targets using Vivado IDE;
• Proficient in development, verification, and debugging of MOSA interfaces/buses (Ethernet, PCIe, AXI4, UART, and SDLC)
• Competency with simulation tools (Questa/ModelSim) and hardware debugging tools (logic analyzers, oscilloscopes).
• Creating and executing verification plans using simulation, analysis, and hardware bench testing.
• Understanding of Open Source VHDL Verification Methodology (OSVVM) or Universal Verification Methodology (UVM). OSVVM preferred

Preferred Qualifications

• MS or PhD in Electrical Engineering, Computer Engineering, or related discipline.
• Active U.S. Government DoD Secret security clearance at the time of application.
• Experience with missile systems, seeker systems, or other high reliability, environmentally challenging electro optical applications.
• Previous experience or knowledge of DoD missile defense programs and associated standards.
• Direct experience with AMD Xilinx Versal Gen 2 or Gen 1
• Advanced experience with both Vivado IDE and Vitis Unified IDE.
• Experience designing, integrating, and verifying DDR memory interfaces (e.g., DDR3/DDR4/DDR5) and fabric‑based controllers (such as AXI or custom interconnects) in FPGA designs, including expertise in IP configuration, timing closure, signal integrity, and high‑throughput data movement.
• Understanding of embedded C/C++ programming for integration with processors/SoCs
• Knowledge of high-speed PCB design and signal integrity
• Strong experience with OSVVM or UVM.

Primary Level Salary Range

$108,200.00 - $162,400.00

The above salary range represents a general guideline; however, Northrop Grumman considers a number of factors when determining base salary offers such as the sc