Senior FPGA Design Engineer (Nextest, Tualatin, OR)

Teradyne; Tualatin (OR); On-site; USD 170,400 - 272,600; Full time

Benefits offered by this job

Discretionary bonus

Comprehensive benefits package

Job summary

Teradyne’s Memory Test Division seeks an FPGA Engineer to develop next‑generation memory test solutions. You will architect FPGA designs for Flash and DRAM test instrumentation, guide junior engineers, and convert complex customer requirements into robust, extensible implementations.

Ideal candidates have 8+ years in FPGA design, strong RTL/Verilog skills, and experience with FPGA tool flows and lab validation. Occasional travel may be required.

Qualifications

• BS/MS in Electrical Engineering or related field.
• 8+ years of relevant work experience in FPGA design.
• Experience in digital design, RTL coding, timing closure and lab validation.

Responsibilities

• Architect and implement FPGA solutions for memory test instrumentation.
• Provide technical guidance to junior engineers.
• Translate customer requirements into reliable designs.
• Maintain and extend existing FPGA designs for quality and new requirements.
• Meet schedule commitments and deliver high‑quality products.
• Occasional travel may be required.

Skills

Digital design

RTL coding

Timing closure

C/C++

Lab validation

Verilog HDL

Familiarity with FPGA tool flows

UVM methodology

Education

B.S. or M.S. in Electrical Engineering or closely related discipline

Tools

Intel/Xilinx FPGA tool flows

Static Timing Analysis tools

Job description

Location

Tualatin, OR, USA; San Jose, CA, USA

Opportunity Overview

Teradyne’s Memory Test Division (MTD) seeks a motivated and technically driven FPGA Engineer to support the development of our growing portfolio of cutting‑edge memory test solutions.

Responsibilities

• Architect and implement FPGA solutions to support next‑generation Flash and DRAM test instrumentation.
• Provide technical guidance to junior engineers.
• Turn abstract concepts and customer requirements into reliable, extensible, and supportable designs.
• Assist in the maintenance and extension of existing FPGA designs to support quality improvement and emerging customer requirements.
• Maintain schedule commitments and deliver high‑quality end products.
• Occasional travel may be required.

All About You

• B.S. or M.S. in Electrical Engineering or closely related discipline and 8+ years of relevant work experience.
• Experience with Digital Design and Architecture.
• RTL coding, synthesis, timing closure and lab validation.
• Experience with Static Timing Analysis of ASICs or FPGAs.
• Experience with digital simulation testbench creation.
• Experience with C or C++.
• Familiarity with lab equipment such as oscilloscopes, power supplies and waveform generators.

Additional Desired Skills

• FPGA Transceiver‑based design experience.
• Experience with DRAM and Flash Memory interfaces.
• Experience with Intel/Xilinx FPGA tool flows.
• Proficiency with Verilog HDL Language.
• Familiarity with UVM Methodology.
• Linux and Windows operating systems experience.
• Familiarity with ATE instrumentation.

Compensation

The base salary range for this role is $170,400 - $272,600. This range is a good faith estimate, and the amount of base salary will correspond with experience and skill set. This range can also fluctuate depending on demand and location.

Incentive Plan

This job is eligible for discretionary bonus(es) based on financial performance.

Benefits

Teradyne offers a variety of robust health and well‑being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more.