Senior FPGA/ASIC Verification Lead — SystemVerilog/UVM

Prattwhitney; Fort Wayne (IN); On-site; USD 90,000 - 120,000; Full time

Job summary

Prattwhitney is seeking a Principal Electrical or Computer Engineer for onsite work in Fort Wayne, IN. This position involves leading the design and verification of advanced testbenches for high-performance digital ASICs and FPGAs supporting critical Mission Systems programs.

The ideal candidate will have a STEM degree with significant experience in VHDL and SystemVerilog, as well as a proven ability to design and execute verification testbenches. U.S. citizenship and a DoD Secret clearance are required.

Qualifications

• Typically requires a STEM degree and minimum 8 years of relevant experience, or an advanced degree and minimum 5 years of experience.
• Demonstrated experience developing and simulating RTL designs using VHDL and/or Verilog.
• Preferred: Experience with ASIC/FPGA lab validation and familiarity with production test concepts.

Responsibilities

• Lead design, implementation, and verification of advanced testbenches for digital ASICs and FPGAs.
• Develop verification environment architecture and design using SystemVerilog.
• Create written test plans, test cases, and tracking coverage metrics.

Skills

VHDL

SystemVerilog

Git

Mentoring

Unix/Linux

Education

STEM degree

Tools

Revision control systems

Job description

Prattwhitney is seeking a Principal Electrical or Computer Engineer for onsite work in Fort Wayne, IN. This position involves leading the design and verification of advanced testbenches for high-performance digital ASICs and FPGAs supporting critical Mission Systems programs.

The ideal candidate will have a STEM degree with significant experience in VHDL and SystemVerilog, as well as a proven ability to design and execute verification testbenches. U.S. citizenship and a DoD Secret clearance are required.