Senior ASIC/FPGA Verification Engineer - Secret Clearance

Prattwhitney; El Segundo (CA); On-site; USD 95,500 - 181,700; Full time

Benefits offered by this job

Medical, dental, and vision insurance

401(k) plan with employer matching

Tuition reimbursement program

Life insurance and disability coverage

Relocation assistance

Job summary

Prattwhitney is seeking a Senior ASIC/FPGA Verification Engineer in El Segundo, CA. The role involves designing and building verification environments using SystemVerilog, developing testbenches for RTL verification, and mentoring junior engineers.

Candidates should possess a degree in STEM with 5+ years of experience, including expertise in VHDL/SystemVerilog. Competitive salary ranges from USD 95,500 to USD 181,700 based on experience and role functions.

Qualifications

• Minimum of 5 years of relevant experience, or an advanced degree with at least 3 years.
• Proven experience developing and simulating RTL designs in a professional environment.
• Demonstrated ability to design and execute verification testbenches.

Responsibilities

• Design and build verification environment architecture using SystemVerilog.
• Develop testbenches for verification of RTL blocks.
• Provide technical guidance and mentorship to junior engineers.

Skills

VHDL

SystemVerilog

RTL design

Git

Communication

Education

Degree in Science, Technology, Engineering or Mathematics (STEM)

Tools

Git

QuestaSim

Quartus

Vivado

Job description

Prattwhitney is seeking a Senior ASIC/FPGA Verification Engineer in El Segundo, CA. The role involves designing and building verification environments using SystemVerilog, developing testbenches for RTL verification, and mentoring junior engineers.

Candidates should possess a degree in STEM with 5+ years of experience, including expertise in VHDL/SystemVerilog. Competitive salary ranges from USD 95,500 to USD 181,700 based on experience and role functions.