Principal FPGA/ASIC Verification Engineer (Onsite)

Prattwhitney; Fort Wayne (IN); On-site; USD 90,000 - 120,000; Full time

Job summary

Prattwhitney is seeking a Principal Electrical or Computer Engineer for onsite work in Fort Wayne, IN. This position involves leading the design and verification of advanced testbenches for high-performance digital ASICs and FPGAs supporting critical Mission Systems programs.

The ideal candidate will have a STEM degree with significant experience in VHDL and SystemVerilog, as well as a proven ability to design and execute verification testbenches. U.S. citizenship and a DoD Secret clearance are required.

Qualifications

• Typically requires a STEM degree and minimum 8 years of relevant experience, or an advanced degree and minimum 5 years of experience.
• Demonstrated experience developing and simulating RTL designs using VHDL and/or Verilog.
• Preferred: Experience with ASIC/FPGA lab validation and familiarity with production test concepts.

Responsibilities

• Lead design, implementation, and verification of advanced testbenches for digital ASICs and FPGAs.
• Develop verification environment architecture and design using SystemVerilog.
• Create written test plans, test cases, and tracking coverage metrics.

Skills

VHDL

SystemVerilog

Git

Mentoring

Unix/Linux

Education

STEM degree

Tools

Revision control systems

Job description

Position Overview

Principal Electrical or Computer Engineer – Onsite, FortWayne, IN (US‑Citizen required). Requires an active and transferable U.S. government‑issued security clearance (DoD Secret). This role leads the design, implementation, and verification of advanced testbenches for a portfolio of high‑performance digital ASICs and FPGAs, supporting critical MissionSystems programs within the Microelectronics Technology team.

Responsibilities

• Verification environment architecture and design using SystemVerilog with OVM/UVM
• Creation of written test plan, test cases, code coverage tracking, and functional coverage tracking
• Testbench development for the verification of RTL blocks using VHDL or SystemVerilog
• Recommend new tools and practices for continuous improvement in the group’s ASIC/FPGA verification flow
• Contribute to engineering estimates for new program pursuits
• Provide technical leadership for project verification teams, breaking down work, planning activities, and reporting status

Qualifications

• Typically requires a STEM degree and minimum 8years of relevant experience, or an advanced degree and minimum 5years of experience
• Demonstrated experience developing and simulating RTL designs using VHDL and/or Verilog in a professional FPGA or ASIC development environment (at least 4years)
• Proven ability to design, implement, and execute verification testbenches for RTL blocks using VHDL and/or SystemVerilog
• Experience with chip‑level verification methodologies (constrained‑random testing, functional coverage analysis, assertion‑based verification)
• Experience using revision control systems such as Git or Subversion
• Demonstrated ability to work independently and mentor junior engineers
• Preferred: Experience with ASIC/FPGA lab validation and debug, familiarity with DFT, manufacturability, and production test concepts, proficiency with Unix/Linux, scripting or software development

Security Clearance

U.S. citizenship required. Active and transferable DoD Secret security clearance required prior to start date.

EEO Statement

RTX is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability or veteran status.