Senior ASIC/FPGA Verification Lead (DoD Secret)

Prattwhitney; Fort Wayne (IN); On-site; USD 130,000 - 190,000; Full time

Benefits offered by this job

Medical Insurance

Three weeks vacation

401(k) plan

Tuition reimbursement

Student loan repayment

Life Insurance

Disability Coverage

Optional coverages

Job summary

RTX in Fort Wayne, IN is seeking a Senior ASIC/FPGA Verification Engineer to design verification environments using SystemVerilog and UVM, develop testbenches, and collaborate with design teams for ASIC/FPGA validation.

The role requires a STEM degree with 5+ years (or advanced degree with 3+ years), DoD Secret clearance, and experience with RTL verification, constrained-random testing, and VHDL/Verilog. Onsite work with strong mentorship within an integrated team.

Qualifications

• Degree in Science, Technology, Engineering or Mathematics (STEM) with 5+ years relevant experience, or an advanced degree with 3+ years.
• Active DoD Secret security clearance required.
• Experience simulating RTL designs using VHDL and/or Verilog in FPGA/ASIC environments.
• Experience designing, implementing, and executing verification testbenches for RTL blocks.
• Knowledge of constrained-random testing, functional coverage, and assertion-based verification.
• Proficiency with revision control tools (Git, Subversion).

Responsibilities

• Design and architect verification environments using SystemVerilog with OVM/UVM.
• Create written test plans, test cases, and track code and functional coverage.
• Develop testbenches for RTL blocks using VHDL or SystemVerilog.
• Collaborate with design engineers for integration and validation of ASIC/FPGA solutions.
• Provide technical guidance and mentorship to junior engineers.
• Lead project verification teams: break down work, plan activities, report status.
• Contribute to engineering estimates for new program pursuits.

Skills

SystemVerilog

Verilog

VHDL

RTL verification

Testbench design

Mentorship

Education

Bachelor's degree in STEM

Advanced degree in STEM

Tools

QuestaSim

Synplify

Quartus

Vivado

Git

Subversion

Job description

RTX in Fort Wayne, IN is seeking a Senior ASIC/FPGA Verification Engineer to design verification environments using SystemVerilog and UVM, develop testbenches, and collaborate with design teams for ASIC/FPGA validation.

The role requires a STEM degree with 5+ years (or advanced degree with 3+ years), DoD Secret clearance, and experience with RTL verification, constrained-random testing, and VHDL/Verilog. Onsite work with strong mentorship within an integrated team.