Security-Cleared FPGA Verification Engineer II

Prattwhitney; Fort Wayne (IN); On-site; USD 90,000 - 130,000; Full time

Benefits offered by this job

Medical insurance

Dental/vision

Vacation 3 weeks

401(k) matching

Tuition assistance

Life and disability

Supplemental insurance

Job summary

Prattwhitney in Fort Wayne, Indiana, onsite, is seeking an experienced verification engineer to design and implement testbenches for high-performance RTL and FPGA blocks used in signal processing and information assurance products.

The role focuses on SystemVerilog/UVM environments, test plan creation, coverage tracking, and leadership of verification activities within a matrixed team. A STEM degree, 2+ years RTL experience, and a Secret clearance are required.

Qualifications

• Degree in STEM or related field.
• Minimum 2 years of RTL coding and simulation in VHDL or Verilog.
• Experience developing testbenches for RTL blocks using VHDL and/or SystemVerilog.
• Familiarity with chip-level verification best practices and languages (constrained random, functional coverage, SystemVerilog).
• Knowledge of revision-control tools such as Git or Subversion.
• Active and transferable U.S. government-issued security clearance (Secret) required on day 1.
• U.S. citizenship required.

Responsibilities

• Architect and design verification environments using SystemVerilog with OVM/UVM.
• Create written test plans, test cases, and track code and functional coverage.
• Develop testbenches for RTL blocks in VHDL or SystemVerilog.
• Contribute to engineering estimates for new program pursuits.
• Provide technical leadership for project verification teams – break down work, plan activities, and report status.

Skills

RTL coding

SystemVerilog

VHDL

Verilog

UVM

Testbenches

C/C++

Unix scripting

Git

Communication

Education

STEM degree

Tools

QuestaSim

Synplify

Quartus

Vivado

Git

Job description

Prattwhitney in Fort Wayne, Indiana, onsite, is seeking an experienced verification engineer to design and implement testbenches for high-performance RTL and FPGA blocks used in signal processing and information assurance products.

The role focuses on SystemVerilog/UVM environments, test plan creation, coverage tracking, and leadership of verification activities within a matrixed team. A STEM degree, 2+ years RTL experience, and a Secret clearance are required.