Senior ASIC/FPGA Verification Lead (SystemVerilog/UVM)

Prattwhitney; Cedar Rapids (IA); On-site; USD 100,000 - 130,000; Full time

Benefits offered by this job

Medical, dental, and vision insurance

401(k) with employer matching

Tuition reimbursement

Life insurance and disability coverage

Employee Assistance Plan

Job summary

Prattwhitney is seeking a Principal Electrical or Computer Engineer in Cedar Rapids, Iowa, to lead the design, implementation, and verification of advanced testbenches for high-performance digital ASICs and FPGAs. Candidates should have at least 8 years of relevant experience and strong knowledge of RTL development using VHDL or SystemVerilog.

This role offers a competitive benefits package that includes medical insurance, 401(k) matching, tuition reimbursement, and various wellness programs.

Qualifications

• 8+ years relevant experience or 5+ with an advanced degree.
• Active U.S. government security clearance required.
• Demonstrated experience with RTL designs in FPGA/ASIC environment.

Responsibilities

• Lead design, implementation, and verification of advanced testbenches.
• Create written test plans and cases for verification.
• Provide technical leadership for project verification teams.

Skills

RTL design development

VHDL

SystemVerilog

Functional verification

Communication skills

Education

Degree in STEM

Advanced degree in related field

Tools

Git

QuestaSim

Quartus

Job description

Prattwhitney is seeking a Principal Electrical or Computer Engineer in Cedar Rapids, Iowa, to lead the design, implementation, and verification of advanced testbenches for high-performance digital ASICs and FPGAs. Candidates should have at least 8 years of relevant experience and strong knowledge of RTL development using VHDL or SystemVerilog.

This role offers a competitive benefits package that includes medical insurance, 401(k) matching, tuition reimbursement, and various wellness programs.