FPGA Verification Engineer Air Dominance and Strike for Fastwater Staffing

Hikinex; Costa Mesa (CA); On-site; USD 100,000 - 130,000; Full time

Job summary

HIKINEX is seeking a FPGA Verification Engineer in Costa Mesa, CA. Responsibilities include architecting UVM verification environments, developing verification plans, and ensuring compliance with safety standards like DO-254. Candidates should have a Bachelor's in Electrical Engineering or related field and 2+ years in FPGA/ASIC verification. Proficiencies in SystemVerilog, UVM, and industry simulators like Questa are essential. A collaborative approach and eligibility for U.S. Secret security clearance are also required.

Qualifications

• 2+ years of experience in FPGA/ASIC verification.
• Proficient in UVM methodology and SVA.
• Eligible to obtain a U.S. Secret security clearance.

Responsibilities

• Architect and implement UVM verification environments.
• Develop verification plans with traceability.
• Author SystemVerilog Assertions for compliance checks.
• Establish and maintain regression suites.
• Collaborate with design engineers on RTL reviews.

Skills

SystemVerilog

UVM methodology

Object-oriented programming

Git-based workflows

Linux development

Communication skills

Teamwork

Education

Bachelor's degree in Electrical Engineering or related field

Tools

Questa

VCS

Xcelium

Vivado

Job description

ABOUT THE JOB

We are looking for a FPGA Verification Engineer to join our rapidly growing team in Costa Mesa, CA. You will own verification of FPGA/SoC designs on AMD (Xilinx) platforms for flight‑critical avionics, with a focus on UVM‑based methodology and coverage‑driven verification. This will require expertise in SystemVerilog, object‑oriented programming, and UVM. If you are someone who has supported rapid avionics development, then this role is for you.

WHAT YOU'LL DO

• Architect and implement UVM verification environments (drivers, monitors, predictors, scoreboards) for AMD (Xilinx) FPGA/SoC designs
• Develop verification plans with traceability to system and hardware requirements
• Author SystemVerilog Assertions (SVA) for protocol compliance and design intent checks
• Build functional coverage models and drive code coverage analysis to closure
• Develop constrained‑random and transaction‑level test sequences to maximize coverage and uncover corner‑case bugs
• Establish and maintain regression suites, tracking coverage metrics and verification progress
• Debug failures using waveform tools and simulation logs at the HDL and system level
• Collaborate with design engineers on RTL reviews, bug resolution, and micro‑architecture refinement
• Support hardware validation and board bring‑up on target platforms
• Ensure verification meets DO‑254 and relevant safety standards
• Author verification closure reports and coverage analysis summaries

REQUIRED QUALIFICATIONS

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field
• 2+ years of experience in FPGA/ASIC verification
• Proficient in SystemVerilog, UVM methodology and SVA, with experience contributing to and extending UVM testbenches
• Object‑oriented programming principles
• Industry simulators (Questa, VCS, Xcelium, or Vivado)
• Git‑based collaborative workflows including code review
• Linux development environments
• Strong communication and teamwork skills
• Eligible to obtain and hold a U.S. Secret security clearance

PREFERRED QUALIFICATIONS

• 5+ years of experience in FPGA/ASIC verification
• Master's degree in Electrical Engineering, Computer Engineering, or related field
• DO‑254, avionics verification standards for UAS, and safety‑critical verification processes
• SVUnit or equivalent unit‑testing frameworks
• Formal verification or CDC verification tools
• Digital interfaces: Ethernet, PCIe, JESD204C, MIL‑STD-1553, SPI
• Verification automation scripting (Python, Tcl, Makefile)
• SoC and ARM‑based embedded platforms
• Verification automation, CI/CD integration, and Nix‑based build environments