FPGA Verification Engineer

Compunnel, Inc.; Mountain View (CA); On-site; USD 100,000 - 130,000; Full time

Job summary

A leading technology firm seeks a skilled FPGA Verification Engineer in Mountain View. This role involves verifying FPGA designs with advanced methodologies and requires strong expertise in SystemVerilog, UVM, and debugging skills. The ideal candidate will develop verification plans, utilize industry-standard tools, and collaborate with cross-functional teams to enhance product quality. Competitive compensation is offered.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
• Strong understanding of FPGA design principles and architectures.
• Proficiency in SystemVerilog, UVM, and scripting languages (Python, Perl).
• Experience with hardware description languages such as VHDL and Verilog.
• Excellent debugging, analytical, and problem-solving skills.

Responsibilities

• Develop and execute verification plans using SystemVerilog and UVM.
• Utilize standard verification tools for simulation and analysis.
• Perform code coverage and functional coverage analysis.
• Debug and resolve design and verification issues efficiently.
• Document verification processes and results.

Skills

SystemVerilog

UVM

Debugging skills

Problem-solving skills

Analytical skills

Communication skills

Education

Bachelor’s or Master’s degree in Electrical Engineering or related field

Tools

QuestaSim

Synopsys VCS

EDA tools from Cadence

Job description

The FPGA Verification Engineer will be responsible for verifying FPGA designs using advanced methodologies and tools.

This role requires strong expertise in SystemVerilog, UVM, and industry-standard verification tools, along with excellent debugging and problem-solving skills.

The engineer will work independently on complex verification tasks and collaborate with cross-functional teams to ensure high-quality deliverables.

Key Responsibilities

• Develop and execute verification plans for FPGA designs using SystemVerilog and UVM methodology.
• Utilize industry-standard verification tools such as QuestaSim and Synopsys VCS for simulation and analysis.
• Perform code coverage and functional coverage analysis to ensure completeness of verification.
• Debug and resolve design and verification issues efficiently.
• Automate verification tasks and create scripts for reporting and process optimization.
• Collaborate with design teams to ensure compliance with functional specifications and design guidelines.
• Document verification processes, results, and best practices.
• Participate in technical discussions, reviews, and contribute to process improvements.

Required Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• Strong understanding of FPGA design principles and architectures.
• Proficiency in SystemVerilog, UVM, and scripting languages (Python, Perl).
• Experience with hardware description languages such as VHDL and Verilog.
• Hands‑on experience with EDA tools from Cadence, Synopsys, or Mentor Graphics.
• Excellent debugging, analytical, and problem‑solving skills.
• Strong communication and collaboration abilities.

Preferred Qualifications

• Familiarity with bus protocols (e.g., AXI, PCIe, USB, Ethernet).
• Knowledge of advanced verification techniques and coverage‑driven methodologies.
• Exposure to physical design, DFT, or mixed‑signal verification concepts.