FPGA/ASIC Verification Engineer - Rochester, NY

MissionHires; City of Rochester (NY); Sur place; USD 100 000 - 130 000; Plein temps

Résumé du poste

MissionHires is looking for an experienced FPGA/ASIC Verification Engineer to verify and validate FPGA-based embedded communication systems. The position involves crafting verification plans, self-checking testbenches using SystemVerilog, and collaborating to meet system requirements.

The ideal candidate will have a Bachelor's degree with significant experience in FPGA/ASIC verification, knowledge of UVM methodologies, and the ability to process security clearances. This role is essential for ensuring the quality and functionality of advanced communication systems.

Qualifications

• 6+ years of relevant FPGA/ASIC verification experience.
• Experience developing embedded system solutions.
• Ability to obtain and maintain US Security Clearance.

Responsabilités

• Perform design verification and validation of FPGA systems.
• Develop detailed verification test plans.
• Create self-checking testbenches using SystemVerilog.
• Collaborate with cross-functional teams.

Connaissances

SystemVerilog

UVM/OVM methodology

FPGA/ASIC development

Debugging FPGA firmware

Scripting (Bash, Python)

Formation

Bachelor's degree or equivalent experience

Description du poste

MissionHires is seeking an experienced FPGA/ASIC Verification Engineer to verify and validate FPGA-based embedded communication systems. You will craft comprehensive verification plans, build self-checking SystemVerilog/UVM environments, drive functional coverage closure, and collaborate cross-functionally to ensure designs meet stringent system requirements. This role includes preparing and presenting technical reviews and may require the ability to obtain and maintain US Security Clearance.

Responsibilities

• Perform FPGA/ASIC design verification and validation of embedded electronic communication systems
• Develop high-level and detailed verification test plans aligned with system requirements and specifications
• Create self-checking testbenches using SystemVerilog for verification and validation
• Develop UVM/OVM components including agents, sequences, covergroups, predictors, and scoreboards
• Author randomized and directed tests to achieve functional coverage goals and provide feedback to the team
• Utilize advanced functional verification tools to collect and report functional coverage
• Collaborate with cross-functional teams to define and verify product and design requirements
• Analyze and debug FPGA firmware and related hardware issues
• Prepare and conduct design and implementation reviews; deliver technical briefings and status updates to internal and external stakeholders
• Work within Linux environments and leverage scripting to automate verification workflows

Requirements

• Bachelor’s degree with 6+ years of relevant experience, or a Master’s degree with 4+ years, or 10+ years of relevant experience in lieu of a degree
• Experience developing and verifying FPGA/ASIC-based embedded system solutions
• Proven proficiency in FPGA/ASIC verification using SystemVerilog
• Working knowledge of UVM/OVM methodology and ability to build reusable verification components
• Experience creating randomized and directed tests and driving functional coverage closure
• Ability to analyze and debug FPGA firmware and related hardware
• Familiarity with Linux OS environments
• Experience with scripting languages such as Bash, Perl, Python, or Tcl
• Ability to obtain and maintain US Security Clearance