Senior FPGA Architect - Satellite Communications

Motion Recruitment; Chandler (AZ); Sur place; USD 140 000 - 190 000; Plein temps

Résumé du poste

Motion Recruitment is seeking a Senior FPGA Engineer for a full-time onsite role in Chandler, Arizona. You will design and develop complex FPGA SoC systems for next-generation satellite communications, including RTL, IP integration, embedded software, and hardware interfaces.

The ideal candidate has 5+ years in FPGA/ASIC SoC design, proficiency with VHDL/Verilog/SystemVerilog, and experience with Vivado or Quartus, AXI/AMBA, PCIe, Ethernet, and TCP/IP.

Qualifications

• 5+ years FPGA/ASIC SoC design and development experience.
• Strong experience with VHDL, Verilog, or SystemVerilog.
• Hands-on with Vivado or Quartus.
• Experience with full FPGA design flows: synthesis, implementation, simulation, debugging.
• Strong knowledge of AXI/AMBA interfaces.
• Experience with high-performance AXI-Stream IP.
• Understanding of STA, timing closure, SDC.
• Experience with high-speed transceivers (PCIe, Ethernet).
• Proficiency in C/C++ and Git.
• Experience FPGA simulations and validation before hardware integration.
• Understanding TCP/IP, UDP protocols.

Responsabilités

• 40% FPGA RTL Development (VHDL/SystemVerilog)
• 25% FPGA SoC Integration (Vivado/Quartus)
• 20% Embedded Software/Firmware Development (C/C++)
• 15% High-Speed Interfaces, Timing Analysis

Connaissances

FPGA/ASIC SoC design

VHDL/SystemVerilog

Vivado/Quartus

AXI/AMBA interfaces

C/C++ programming

Git version control

Timing analysis

Ethernet/Networking protocols

Formation

Bachelor's degree in Electrical/Computer Engineering

Outils

Xilinx Vivado

Intel/Altera Quartus

Description du poste

Motion Recruitment is seeking a Senior FPGA Engineer for a full-time onsite role in Chandler, Arizona. You will design and develop complex FPGA SoC systems for next-generation satellite communications, including RTL, IP integration, embedded software, and hardware interfaces.

The ideal candidate has 5+ years in FPGA/ASIC SoC design, proficiency with VHDL/Verilog/SystemVerilog, and experience with Vivado or Quartus, AXI/AMBA, PCIe, Ethernet, and TCP/IP.