Senior FPGA Engineer / Onsite / Chandler

Motion Recruitment; Chandler (AZ); On-site; USD 140,000 - 190,000; Full time

Job summary

Motion Recruitment is seeking a Senior FPGA Engineer for a full-time onsite role in Chandler, Arizona. You will design and develop complex FPGA SoC systems for next-generation satellite communications, including RTL, IP integration, embedded software, and hardware interfaces.

The ideal candidate has 5+ years in FPGA/ASIC SoC design, proficiency with VHDL/Verilog/SystemVerilog, and experience with Vivado or Quartus, AXI/AMBA, PCIe, Ethernet, and TCP/IP.

Qualifications

• 5+ years FPGA/ASIC SoC design and development experience.
• Strong experience with VHDL, Verilog, or SystemVerilog.
• Hands-on with Vivado or Quartus.
• Experience with full FPGA design flows: synthesis, implementation, simulation, debugging.
• Strong knowledge of AXI/AMBA interfaces.
• Experience with high-performance AXI-Stream IP.
• Understanding of STA, timing closure, SDC.
• Experience with high-speed transceivers (PCIe, Ethernet).
• Proficiency in C/C++ and Git.
• Experience FPGA simulations and validation before hardware integration.
• Understanding TCP/IP, UDP protocols.

Responsibilities

• 40% FPGA RTL Development (VHDL/SystemVerilog)
• 25% FPGA SoC Integration (Vivado/Quartus)
• 20% Embedded Software/Firmware Development (C/C++)
• 15% High-Speed Interfaces, Timing Analysis

Skills

FPGA/ASIC SoC design

VHDL/SystemVerilog

Vivado/Quartus

AXI/AMBA interfaces

C/C++ programming

Git version control

Timing analysis

Ethernet/Networking protocols

Education

Bachelor's degree in Electrical/Computer Engineering

Tools

Xilinx Vivado

Intel/Altera Quartus

Job description

A leading global telecommunications and satellite communications company is hiring a Senior FPGA Engineer for a full-time opportunity onsite in Chandler, Arizona. This organization develops advanced communication systems supporting commercial, government, and defense applications. The position focuses on designing and developing complex FPGA System-on-Chip (SoC) systems for next-generation satellite communications, including high-performance RTL development, FPGA IP integration, embedded firmware, and hardware/software interfaces.

Required Skills & Experience

• 5+ years of FPGA/ASIC SoC design and development experience.
• Strong experience developing FPGA designs using VHDL, Verilog, or SystemVerilog.
• Hands-on experience with Xilinx Vivado or Intel/Altera Quartus.
• Experience with complete FPGA design flows, including synthesis, implementation, simulation, and debugging.
• Strong knowledge of AMBA interfaces, including AXI and APB protocols.
• Experience developing high-performance, pipelined AXI-Stream IP.
• Understanding of Static Timing Analysis (STA), timing closure, and Synopsys Design Constraints (SDC).
• Experience analyzing timing reports and resolving critical timing paths.
• Experience with high-speed transceiver interfaces such as PCIe, Ethernet, or related protocols.
• Proficiency in C/C++ programming and Git version control.
• Experience developing FPGA simulations and validating designs before hardware integration.
• Understanding of Ethernet and networking protocols, including TCP/IP, UDP, and related standards.
• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related discipline.

Desired Skills & Experience

• Experience with satellite communications systems and SATCOM waveforms.
• Knowledge of digital IF streaming standards such as VITA 49.2, DIFI, or eCPRI.
• Experience with Embedded Linux, Yocto, U-Boot, or Device Tree.
• Understanding of DVB-S2X or 5G NTN communications technologies.
• Experience with partial FPGA reconfiguration or Dynamic Function eXchange (DFX).
• Experience developing firmware for embedded microcontrollers.
• Knowledge of high-speed networking interfaces supporting 1G through 100G Ethernet.
• Experience contributing to FPGA-related PCB schematic capture and layout.
• Understanding of communications security and zero-trust environments.
• Active DoD security clearance or ability to obtain one.

What You Will Be Doing

Tech Breakdown

• 40% FPGA RTL Development (VHDL/SystemVerilog)
• 25% FPGA SoC Integration and Implementation (Vivado/Quartus)
• 20% Embedded Software and Firmware Development (C/C++)
• 15% High-Speed Interfaces, Networking, and Timing Analysis

Daily Responsibilities

• 70% Hands-On FPGA Design, Development, and Debugging
• 20% Cross-Functional Engineering Collaboration
• 10% Technical Documentation and Design Reviews

The Offer

• Full-time employment
• Onsite in Chandler, Arizona, five days per week
• Competitive base salary based on experience
• Opportunity to work on advanced FPGA and satellite communications technology

Posted By: Isabella Sweet