Senior FPGA Engineer

Employee Relations Associates, Inc.; Chandler (AZ); Hybrid; USD 120,000 - 180,000; Full time

Benefits offered by this job

Medical benefits

Dental benefits

Vision benefits

Life insurance

401(k)

Holiday pay

Job summary

Employee Relations Associates, Inc. in Chandler, AZ is seeking a Senior FPGA Engineer to lead the design, development, and debugging of FPGA SoC systems for advanced satellite communications.

The role emphasizes IP integration, high-performance RTL, and userspace driver/firmware development. Requirements include 5+ years in FPGA/ASIC SoC design, hands-on experience with Quartus or Vivado, and strong C/C++, with a focus on timing, validation, and cross‑functional collaboration in a secure

Qualifications

• 5+ years of FPGA/ASIC SoC design experience.
• Hands-on design, synthesis, and debugging for FPGA systems.
• Experience with IP integration and SOC development.

Responsibilities

• Lead FPGA SoC design, development, and debugging.
• Develop high-performance RTL and firmware for embedded MPUs.
• Create and validate userspace drivers for FPGA IP.

Skills

RTL design & debugging

C/C++

Git

Cross‑functional teamwork

High-level FPGA architecture

Education

Bachelor's degree in Electrical or Computer Engineering

Tools

Quartus (Altera)

Vivado (Xilinx)

AMBA AXI/APB interfaces

Job description

Location: Chandler, AZ (Onsite 5 days/week)
OPEN TO RELOCATION

Position Summary

We are seeking a Senior FPGA Engineer with experience across the entire design flow for complex FPGAs to lead the design, development, and debugging of FPGA SoC systems supporting advanced satellite communications technologies. This role focuses on advanced IP integration, high-performance RTL development, and userspace driver/firmware development.

Responsibilities

• Design, develop, document, debug, and test FPGA SoC systems, including:
  • IP integration into FPGA projects (synthesis and implementation)
  • High-performance FPGA IP development (VHDL/SystemVerilog)
  • Userspace drivers for FPGA IP (C++)
  • Firmware for embedded microcontrollers (C)
• Collaborate effectively with engineering teams and leadership throughout the development lifecycle.
• Support the design, implementation, validation, and optimization of complex FPGA solutions.

Required Qualifications

• Strong digital design experience with FPGA/ASIC SoC development.
• Hands‑on FPGA implementation experience using Client (Altera) Quartus or Xilinx Vivado.
• Experience designing and debugging SoC systems utilizing AMBA AXI and APB interfaces.
• Experience developing high‑throughput, pipelined AXI‑Stream IP optimized for performance.
• Ability to create RTL simulations to identify and resolve issues prior to hardware testing.
• Strong understanding of Static Timing Analysis (STA) and Synopsis Design Constraints (SDC).
• Experience analyzing timing reports and post‑synthesis placement/routing to resolve timing violations.
• Experience contributing to FPGA portions of PCB schematic capture and board layout.
• Experience implementing at least one high‑speed serial protocol, such as:
  • PCI Express
  • Interlaken
  • USB SuperSpeed
  • 1000BASE‑X / SGMII
  • 10GBASE‑R
  • 40GBASE‑4
  • 100GBASE‑R4
• Experience implementing networking protocols including:
  • Layer 1: IEEE 802.3 Ethernet standards (1G–100G)
  • Layer 2/3: IPv4, IPv6, ARP, ICMP, IGMP, UDP, TCP
  • Layer 4: VITA 49.2, DIFI, and/or eCPRI (highly preferred)
• Proficiency in:
  • C
  • C++
  • Git version control
• Strong Microsoft Office skills.
• Experience supporting cross‑functional engineering teams.

Preferred Qualifications

• Knowledge of digital IF standards including VITA 49.2, DIFI, or eCPRI.
• Experience with Embedded Linux, including:
  • Linux Kernel
  • Yocto
  • U‑Boot
  • Device Tree
• Familiarity with SATCOM waveforms such as:
  • DVB‑S2X
  • 5G NTN (3GPP Release 17/18)
• Understanding of secure communications and Zero Trust architectures.
• Experience with:
  • Partial Reconfiguration (DFX)
  • PCIe CvP
• Active DoD Security Clearance or ability to obtain one.

Education

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.

Experience

• 5+ years of FPGA/ASIC SoC design experience.

TalentBridge employees are eligible for many benefit offerings such as medical, dental, vision, life insurance, short term disability, 401(k) and holiday pay!