Senior FPGA Engineer: Satellite SoC & High-Speed Interfaces

Owen Daniels; Arizona; On-site; USD 120,000 - 180,000; Full time

Benefits offered by this job

Vacation time

Personal time

Sick leave

Holidays

Medical/dental/vision

Job summary

A global leader in Satellite and Space technology is hiring an FPGA Engineer to join their Platforms and FPGA SoC Group in Arizona. You'll lead the design, development, and debug of complex FPGA SoC systems for satellite communications—from IP integration through high‑performance RTL and firmware.

The ideal engineer has senior experience with at least 5 years in the field. Responsibilities include hands‑on RTL design and verification, timing, and interface familiarity (AMBA AXI/APB, PCIe,

Qualifications

• BS in EE, CS, or equivalent.
• 5+ years' industry experience
• Strong hands-on with Xilinx Vivado and Altera Quartus
• SoC debug experience with AMBA AXI/APB interfaces
• RTL simulation, SDC, timing analysis
• Gigabit transceiver protocols (PCIe, Interlaken, USB SuperSpeed, 10/40/100G)
• Network protocols (Ethernet, IPv4/IPv6, TCP/UDP)
• Embedded C/C++, microcontrollers, Git
• Bonus: Embedded Linux (Kernel/Yocto/U-Boot/DeviceTree)

Responsibilities

• Lead design, development, and debug of FPGA SoC systems for satellite comms.
• Integrate IP and develop high‑performance RTL and firmware.
• Verify timing and interfaces (AMBA AXI/APB).
• Collaborate cross‑functionally with hardware and software teams.

Skills

FPGA design

RTL debugging

Embedded C/C++

Git

AMBA AXI/APB

Network protocols

SoC debugging

PCIe

Education

BS in EE/CS

Tools

Xilinx Vivado

Altera Quartus

ModelSim/QuestaSim

Yocto/U-Boot/DeviceTree

Job description

A global leader in Satellite and Space technology is hiring an FPGA Engineer to join their Platforms and FPGA SoC Group in Arizona. You'll lead the design, development, and debug of complex FPGA SoC systems for satellite communications—from IP integration through high‑performance RTL and firmware.

The ideal engineer has senior experience with at least 5 years in the field. Responsibilities include hands‑on RTL design and verification, timing, and interface familiarity (AMBA AXI/APB, PCIe,