Senior FPGA Engineer

GCS Recruitment; Beaverton (OR); On-site; USD 130,000 - 190,000; Full time

Job summary

GCS Recruitment partners with a leading aerospace/communications org to hire a Senior FPGA Engineer in Beaverton, Oregon. You will design and deliver advanced FPGA solutions for a next‑gen satellite communication system, collaborating with system architects and cross‑functional teams.

You will own FPGA bitstreams, develop with Verilog/SystemVerilog, perform timing closure, validation, and production release, and help with hardware bring‑up, tests, and documentation.

Qualifications

• 7+ years of hands-on FPGA design experience.
• Strong expertise with Verilog HDL for RTL design and verification.
• Experience designing with AMD Xilinx Versal ACAP and Microchip IGLOO2.
• Proficiency with FPGA development tools (Vivado, Libero SoC).
• Ability to work with system architects and cross-functional teams.

Responsibilities

• Own the development and delivery of one or more FPGA bitstreams.
• Design, develop, and implement complex FPGA architectures using Verilog HDL.
• Lead FPGA development across the complete lifecycle: microarchitecture, RTL design, timing closure.
• Perform synthesis, place & route, timing analysis, and design optimization.
• Develop testbenches, simulate, and validate FPGA designs in hardware and lab.
• Collaborate with hardware, firmware, and software teams to validate FPGA solutions.
• Support manufacturing, production deployment, and post-release engineering activities.

Skills

Verilog HDL

SystemVerilog

Python

TCL

Perl

Problem solving

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field

Tools

Xilinx Vivado

Libero SoC

ModelSim

Vivado Simulator

VCS

Git

SVN

Job description

Job Title: Senior FPGA Engineer

About the Role:

We are seeking an experienced Senior FPGA Engineer to design and develop advanced FPGA solutions for a next-generation satellite communication system. This is a unique opportunity to contribute to the development of cutting-edge networking technology with minimal legacy constraints. You will work closely with system architects and cross-functional engineering teams to define, implement, validate, and release FPGA-based solutions supporting high-performance communication systems.

Key Responsibilities:

• Own the development and delivery of one or more FPGA bitstreams.
• Design, develop, and implement complex FPGA architectures using Verilog HDL.
• Lead FPGA development across the complete lifecycle, including:
• Microarchitecture
• RTL Design
• Physical Implementation
• Timing Closure
• Simulation & Verification
• Lab Validation
• Production Release
• Develop FPGA-based networking and digital communication functions.
• Collaborate with system architects, hardware engineers, firmware, and software teams to implement and validate FPGA solutions.
• Build FPGA prototypes to evaluate architecture and design tradeoffs.
• Support hardware bring-up, system integration, and debugging involving FPGA, RF, firmware, and networking components.
• Perform synthesis, place & route, timing analysis, and design optimization.
• Develop comprehensive testbenches and simulation environments.
• Debug FPGA designs in both simulation and hardware environments.
• Drive design tradeoff analysis focused on performance, power, cost, area, and customer experience.
• Create technical documentation including design specifications, verification plans, and test documentation.
• Support manufacturing, production deployment, and post-release engineering activities.

Required Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field.
• 7+ years of hands-on FPGA design experience.
• Strong expertise with Verilog HDL for RTL design and verification.
• Experience designing with AMD Xilinx Versal ACAP FPGA architecture.
• Experience working with Microchip IGLOO2 FPGA platforms.
• Proficiency with FPGA development tools such as:
• Xilinx Vivado
• Microchip Libero SoC
• Strong understanding of:
• Digital logic design
• Timing analysis and timing closure
• Clock Domain Crossing (CDC)
• Experience with simulation tools such as:
• ModelSim
• Vivado Simulator
• VCS (or equivalent)
• Experience using scripting languages such as Python, TCL, or Perl for design automation.
• Strong debugging, analytical, and problem-solving skills.
• Understanding of industry-standard communication protocols.

Preferred Qualifications:

• Experience with SystemVerilog and UVM verification methodologies.
• Experience with high-speed interfaces including:
• PCIe
• DDR
• Ethernet
• SerDes
• Familiarity with embedded systems and hardware/software integration.
• Experience using version control systems such as Git or SVN.
• Background in digital communications, networking, or signal processing.
• Experience working with DO-254 or other safety-critical design standards.

Required Technical Skills:

• HDL Languages: Verilog (required), SystemVerilog (preferred)
• FPGA Platforms: AMD Xilinx Versal ACAP, Microchip IGLOO2
• Design Tools: Vivado, Libero SoC
• Simulation: ModelSim, Vivado Simulator, VCS (or equivalent)
• Scripting: Python, TCL, Perl
• Version Control: Git, SVN
• Protocols: Industry-standard communication protocols
• Design Expertise: RTL Design, FPGA Verification, Timing Closure, CDC Analysis, Physical Implementation, Hardware Bring-up