Senior FPGA Architect: High-Throughput, Low-Latency Systems

Multibeam Corporation; Sunnyvale (CA); Hybrid; USD 140,000 - 230,000; Full time

Job summary

Multibeam Corporation in Sunnyvale, CA is seeking an experienced FPGA engineer to design, prototype and debug timing-critical mixed-signal electronics for maskless lithography systems. You will work closely with analogue and software engineers to push high-throughput, reliable FPGA implementations from concept to production.

The ideal candidate has 8+ years of production FPGA experience, deep HDL expertise (SystemVerilog/Verilog/VHDL) and a strong grasp of timing closure, CDC, and multi-clock

Qualifications

• 8+ years of hands-on FPGA design experience in production environments.
• Expert command of SystemVerilog, Verilog and/or VHDL.
• Deep understanding of clocking architectures, CDC analysis, and multi-clock systems.
• Strong timing closure skills and XDC/SDC constraints.
• Experience with high-reliability, low-latency digital systems and verification.

Responsibilities

• Design, prototype and debug hardware/software for high precision, timing critical systems.
• Collaborate with analogue and software engineers to deliver integrated solutions.
• Lead end-to-end FPGA architecture decisions from concept through production.
• Support verification, bring-up and validation on custom boards and subsystems.

Skills

HDL design

SystemVerilog

Verilog

VHDL

PCIe integration

DDR3/4/5 interfaces

Clocking architectures

Timing closure

System-level debugging

Embedded processors (MicroBlaze/Nios/3

Tools

Vivado

Git

CI pipelines

Regression testing

Linting tools

ILA/SignalTap

Oscilloscopes

Job description

Multibeam Corporation in Sunnyvale, CA is seeking an experienced FPGA engineer to design, prototype and debug timing-critical mixed-signal electronics for maskless lithography systems. You will work closely with analogue and software engineers to push high-throughput, reliable FPGA implementations from concept to production.

The ideal candidate has 8+ years of production FPGA experience, deep HDL expertise (SystemVerilog/Verilog/VHDL) and a strong grasp of timing closure, CDC, and multi-clock