Senior FPGA/ASIC Design Engineer: High-Speed Systems

MRL Consulting Group | Global Niche Technology Recruitment; Irvine (CA); On-site; USD 140,000 - 190,000; Full time

Job summary

MRL Consulting Group | Global Niche Technology Recruitment is seeking a Senior Hardware Design Engineer in Irvine, CA to lead FPGA/ASIC design efforts. Responsibilities include RTL implementations, block/system-level testbenches, and deployment on FPGA platforms for validation and integration.

The candidate should have 5+ years of experience, expert Verilog/SystemVerilog skills, and a strong background in digital design for high-speed applications.

Qualifications

• Expert knowledge of Verilog and SystemVerilog for complex ASIC/FPGA development.
• Minimum 5 years of industry experience delivering FPGA/ASIC solutions including high-speed interfaces.
• Strong background in digital design for ASIC/FPGA technologies.
• Proven ability to deliver high-quality designs within demanding schedules.
• Experience optimizing timing, area, and performance for high-throughput applications.
• Knowledge of power management techniques, synthesis, and timing analysis.
• Experience with IP verification using UVM.
• Experience with C++/SystemC modelling for system integration.

Responsibilities

• Designing micro-architectures and RTL implementations to meet requirements from Architecture teams.
• Implementing FPGA/ASIC designs using industry-standard methodologies and testbenches.
• Deploying designs onto FPGA platforms for validation and integration.
• Contributing to engineering best practices and design techniques to improve efficiency and quality.
• Collaborating with cross-functional teams to ensure successful project delivery.

Skills

Verilog/SystemVerilog

FPGA/ASIC design

High-speed interfaces (PCIe/JESD)

C++/SystemC modelling

Python scripting

EDA tools (simulation/verification/s​;

Timing closure optimization

Power management techniques

Job description

MRL Consulting Group | Global Niche Technology Recruitment is seeking a Senior Hardware Design Engineer in Irvine, CA to lead FPGA/ASIC design efforts. Responsibilities include RTL implementations, block/system-level testbenches, and deployment on FPGA platforms for validation and integration.

The candidate should have 5+ years of experience, expert Verilog/SystemVerilog skills, and a strong background in digital design for high-speed applications.