Low-Latency FPGA Engineer

Quantiq; Chicago (IL); On-site; USD 130,000 - 190,000; Full time

Job summary

Quantiq is seeking a Hardware Developer to design, optimize, and maintain our high‑performance network paths and FPGA data processing platform. You will work with a team to push digital logic design, IP optimization, and software interfacing drivers toward maximum latency‑sensitive performance.

You should bring 5+ years in hardware development, strong Verilog/SystemVerilog/VHDL and C/C++ abilities, and experience with Xilinx Vivado, FPGAs, and IP.

Qualifications

• 5+ years in Hardware Development or equivalent experience in low-latency environments.
• Familiar with network protocols and hardware build scripting.
• Proficient with Xilinx Vivado, FPGAs and IP cores.
• Advanced Verilog, SystemVerilog or VHDL and C/C++ skills.

Responsibilities

• Architect and develop low-latency modules and platforms in Verilog/VHDL with multiple clock domains.
• Design custom network protocol drivers in C++, focusing on performance and memory optimization.
• Document architecture decisions and optimization strategies for knowledge sharing.
• Debug and profile new and legacy code to maintain peak performance.
• Evaluate system performance and refine technical operations.
• Write high-quality, efficient code (Verilog/VHDL and C/C++).

Skills

Communication skills

Collaboration

Problem solving

Adaptability

Tools

Xilinx Vivado

FPGAs

Verilog/SystemVerilog/VHDL

C/C++

Job description

Quantiq is seeking a Hardware Developer to design, optimize, and maintain our high‑performance network paths and FPGA data processing platform. You will work with a team to push digital logic design, IP optimization, and software interfacing drivers toward maximum latency‑sensitive performance.

You should bring 5+ years in hardware development, strong Verilog/SystemVerilog/VHDL and C/C++ abilities, and experience with Xilinx Vivado, FPGAs, and IP.