Senior Emulation & Verification Engineer for SoC Accel

iTechStack Inc; San Francisco (CA); On-site; USD 140,000 - 210,000; Full time

Job summary

iTechStack Inc. in the Bay Area is seeking a Senior Emulation/Verification Engineer to lead pre-silicon validation using hardware emulation and simulation acceleration.

The role focuses on Cadence Palladium and Synopsys ZeBu environments and requires strong SystemVerilog/UVM expertise and cross-functional collaboration. You will port verification environments, optimize performance, enable long-running regressions, integrate VIPs, and work with RTL, DV, architecture, firmware, and software teams

Qualifications

• Bachelor's or Master's in Electronics/EE/CE/CS.
• 10+ years in Design Verification, Hardware Emulation, or Simulation Acceleration for ASIC/SoC.
• Strong expertise with Cadence Palladium and/or Synopsys ZeBu.
• Proficient in SystemVerilog, UVM, and hardware emulation.
• Experience porting verification environments to acceleration platforms.
• Proficient in Python, Perl, Tcl, or Shell scripting.

Responsibilities

• Maintain and optimize simulation acceleration and emulation environments.
• Port SystemVerilog/UVM verification environments to hardware platforms.
• Partition verification environments between host and emulator.
• Optimize verification to reduce compile time and improve performance.
• Enable long-running regressions and software-driven validation on emulation platforms.
• Integrate third-party Verification IP (VIP) and develop custom transactors.
• Debug RTL, testbench, and emulation issues using waveform analysis.
• Collaborate with RTL, Design Verification, Architecture, Firmware, and Software teams to accelerate project delivery.

Skills

SystemVerilog/UVM

RTL debugging

Waveform analysis

Regression automation

Collaboration

Python scripting

Hardware emulation

Simulation acceleration

Pre-silicon verification

Cohesive verification strategy

Education

Bachelor's or Master's in Electronics/EE/CE/CS

Tools

Cadence Palladium

Synopsys ZeBu

Job description

iTechStack Inc. in the Bay Area is seeking a Senior Emulation/Verification Engineer to lead pre-silicon validation using hardware emulation and simulation acceleration.

The role focuses on Cadence Palladium and Synopsys ZeBu environments and requires strong SystemVerilog/UVM expertise and cross-functional collaboration. You will port verification environments, optimize performance, enable long-running regressions, integrate VIPs, and work with RTL, DV, architecture, firmware, and software teams