Hybrid Senior Design Verification Engineer (Emulation)

Hewlett Packard Enterprise; Sunnyvale (CA); Hybrid; USD 154,000 - 311,000; Full time

Job summary

Hewlett Packard Enterprise in Sunnyvale, CA seeks a Senior Design Verification Engineer specializing in emulation-based verification to drive system-level verification ahead of silicon tape-out. You will build robust UVM testbenches, run constrained-random tests, and validate with emulation platforms such as Palladium/ZeBu/Veloce.

The role emphasizes collaboration with design and validation teams, coverage goals, and early software bring-up on hardware accelerators in a hybrid work model.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science.
• 5–8 years of professional experience in design verification of digital/mixed-signal designs.
• Strong proficiency in SystemVerilog and UVM methodology.
• Hands-on experience with emulation-based verification platforms (Cadence Palladium, Synopsys ZeBu, or Mentor Veloce).
• Solid understanding of digital design concepts including RTL design, synthesis constraints, and timing.
• Experience with constrained-random verification, functional coverage, and code coverage-driven methodologies.
• Proficiency in debugging complex hardware designs using simulation and emulation tools.
• Familiarity with scripting languages such as Python, Perl, or TCL for automation and flow development.
• Strong analytical and problem-solving skills with excellent attention to detail.

Responsibilities

• Develop and execute verification plans for IP-level and system-level designs.
• Build, maintain, and enhance UVM/SystemVerilog-based testbench environments including scoreboards, monitors, drivers, and coverage models.
• Develop and run directed and constrained-random test cases to achieve functional and code coverage goals.
• Set up, configure, and run designs on emulation platforms for system-level verification and performance validation.
• Collaborate with design teams to define verification strategies, review specifications, and identify corner cases and potential design risks.
• Debug complex design issues using waveform analysis, log analysis, and emulation platform debug tools.
• Develop and maintain assertion-based verification to complement simulation and emulation efforts.
• Drive coverage closure and generate verification sign-off reports.
• Support software and firmware teams with early bring-up activities on emulation platforms.
• Continuously improve verification processes, flows, and infrastructure.

Skills

SystemVerilog

UVM

Emulation platforms

Python

Perl

TCL

RTL design

Synthesis constraints

Timing analysis

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science

Master's degree (preferred)

Tools

Cadence Palladium

Synopsys ZeBu

Mentor Veloce

Job description

Hewlett Packard Enterprise in Sunnyvale, CA seeks a Senior Design Verification Engineer specializing in emulation-based verification to drive system-level verification ahead of silicon tape-out. You will build robust UVM testbenches, run constrained-random tests, and validate with emulation platforms such as Palladium/ZeBu/Veloce.

The role emphasizes collaboration with design and validation teams, coverage goals, and early software bring-up on hardware accelerators in a hybrid work model.