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River AI seeks an emulation-focused design verification engineer to drive IP/SoC verification on emulation platforms. You will translate architectural definitions into emulation workloads, run tests, and partner with DV block owners on debug and signoff.
You will build models and infrastructure to support this work, ensuring traceable results across teams. The role requires expertise in SystemVerilog, C/C++, and scripting, with hands-on experience on Palladium/Protium or ZeBu/HAPS.
River AI seeks an emulation-focused design verification engineer to drive IP/SoC verification on emulation platforms. You will translate architectural definitions into emulation workloads, run tests, and partner with DV block owners on debug and signoff.
You will build models and infrastructure to support this work, ensuring traceable results across teams. The role requires expertise in SystemVerilog, C/C++, and scripting, with hands-on experience on Palladium/Protium or ZeBu/HAPS.